PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 499

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.4
The modes where an external event trigger pulse ends
sampling
(SSRC2:SSRC0 = 001, 010 or 011) may be used in
combination with auto-sampling (ASAM = 1) to cause
the ADC to synchronize the sample conversion events
to the trigger pulse source. For example, where
SSRC = 010 and ASAM = 1, the ADC will always end
sampling and start conversions synchronously with the
timer compare trigger event. The ADC will have a
sample conversion rate that corresponds to the timer
comparison event rate.
22.3.5
Sampling can be started manually or automatically
when the previous conversion is complete.
22.3.5.1
Clearing the ASAM (AD1CON1<2>) bit disables the
Auto-Sample mode. Acquisition will begin when the
SAMP (AD1CON1<1>) bit is set by software. Acquisi-
tion will not resume until the SAMP bit is once again
set.
22.3.5.2
Setting the ASAM (AD1CON1<2>) bit enables the
Auto-Sample mode. In this mode, the sampling will
start automatically after the pervious sample has been
converted.
22.3.6
The user can select the voltage reference for the ADC
module. The reference can be internal or external.
The VCFG<2:0> control bits (AD1CON2<15:13>)
select the voltage reference for A/D conversions. The
upper voltage reference (V
reference (V
voltage rails, or the V
22.3.7
The ADC module has the ability to scan through a
selected
(AD1CON2<10>) enables the MUX A input to be
scanned across a selected number of analog inputs.
© 2008 Microchip Technology Inc.
vector
SELECTING THE VOLTAGE
SYNCHRONIZING ADC
OPERATIONS TO INTERNAL OR
EXTERNAL EVENTS
SELECTING AUTOMATIC OR
MANUAL SAMPLING
REFERENCE SOURCE
SELECTING THE SCAN MODE
R
Manual
Automatic
-) may be the internal AV
and
of
REF
+ and V
inputs.
R
+) and the lower voltage
starts
REF
The
- input pins.
DD
CSCNA
conversion
and AV
Preliminary
SS
bit
22.3.7.1
Scan
(AD1CON2<10>). When Scan mode is enabled, the
positive input of MUX A is controlled by the contents of
the AD1CSSL register. Each bit in the AD1CSSL
register corresponds to an analog input. Bit 0 corre-
sponds to AN0, bit 1 corresponds to AN1 and so on. If
a particular bit in the AD1CSSL register is ‘1’, the
corresponding input is part of the scan sequence.
22.3.7.2
The Scan and Alternate modes may be combined to
allow a vector of inputs to be scanned and a single
input to be converted every other sample.
This mode is enabled by setting the CSCNA bit = 1,
and setting the ALTS (AD1CON2<0>) bit = 1.
The CSCNA bit enables the scan for MUX A, and the
CH0SB<3:0>
(AD1CHS<31>) are used to configure the inputs to
MUX B. Scanning only applies to the MUX A input
selection. The MUX B input selection, as specified by
CH0SB<3:0>, will still select a single input.
22.3.8
The SMPI<3:0> bits (AD1CON2<5:2>) select how
many A/D conversions will take place before a CPU
interrupt is generated. This also defines the number of
locations that will be written in the result buffer stating
with ADC1BUF0 (ADC1BUF0 or ADC1BUF8 for Dual
Buffer mode). This can vary from 1 sample to 16 sam-
ples (1 to 8 samples for Dual Buffer mode). After the
interrupt is generated, the sampling sequence restarts;
with the result of the first sample being written to the
first buffer location.
The data in the result registers will be overwritten by the
next sampling sequence. The data in the result buffer
must be read before the completion of the first sample
after the interrupt is generated.
mode
PIC32MX3XX/4XX
SETTING THE NUMBER OF
CONVERSIONS PER INTERRUPT
Scan Mode Enable
Using Scan and Alternate Modes
Together
is
(AD1CHS<27:24>)
enabled
by
DS61143C-page 497
setting
and
CSCNA
CH0NB