PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 230

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
10.2.1
Event: Any system event that can initiate or abort a
DMA transfer.
Transaction: A single-word transfer (up to 4 bytes),
comprised of read and write operations.
Cell Transfer: The number of bytes transferred when
a DMA channel has a transfer initiated before waiting
for another event (given by the DCHCSIZ register). A
cell transfer comprises one or more transactions.
Block Transfer: Defined as the number of bytes trans-
ferred when a channel is enabled. The number of bytes
is the larger of either DCHxSSIZ or DCHxDSIZ. A block
transfer comprises one or more cell transfers.
10.3
Basic Transfer mode transfer features:
• The transfer size is limited to a maximum of 256
• The Source and Destination Pointers wrap around
• A block transfer is complete when the block size
• A DMA event will transfer cell size (DCHxCSIZ)
DS61143C-page 228
bytes transferred per channel.
based on the selected source and destination
size.
bytes have been transferred. The block size is the
larger of source and destination sizes:
- blockSize = max (DCHxSSIZ, DCHxDSIZ).
bytes from source to destination. However, if
DCHxCSIZ is greater than the block size, then
just block size bytes will be transferred.
Basic Transfer Mode
DMA CONTROLLER
TERMINOLOGY
Preliminary
10.3.1
Microchip recommends taking the following steps to
configure a DMA transfer:
• Disable the DMA channel interrupts in the INT
• Clear any existing channel interrupt flags in the
• Enable the DMA controller (if not already
• Set Channel Control register: Priority,
• Set the channel event control: clear/set the events
• If using a pattern match, set the pattern in the
• Set the transfer source and destination physical
• Set the source and destination sizes (DCHxSSIZ,
• Set the cell transfer size (DCHxCSIZ).
• Clear any existing event flag in the DCHxINT
• If using interrupts:
• Enable the selected DMA channel with CHEN
• If not using system events to start the DMA
• Until the DMA transfer is complete you can do
• If transfer complete interrupts (cell complete,
• Otherwise, the DMA channel can be polled to see
Refer to Example 10-1.
controller.
INT controller.
enabled) in DMACON register.
Auto-Enable mode, etc., in DCHxCON. (Don’t
enable the channel yet!)
starting and aborting the transfer. If needed, also
set the pattern match enable in DCHxECON.
DCHxDAT register.
addresses (DCHxSSA and DCHxDSA registers).
DCHxDSIZ registers).
register.
- Set the conditions that will generate an inter-
- Set the DMA channel interrupt priority and
- Enable the DMA channel interrupt in the INT
(DCHxCON<7>).
transfer use CFORCE (DCHxECON<7>) to start
transfer.
some other processing.
block complete, etc.) are enabled, a notification
will be presented in the ISR that the DMA transfer
completed.
if the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
rupt in the DCHxINT register (at least error
interrupt enable and abort interrupt enable,
usually block complete interrupt).
subpriority in the INT controller.
controller.
BASIC TRANSFER MODE
CONFIGURATION
© 2008 Microchip Technology Inc.