PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 388

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
17.2.3
In Slave mode, data from the SPIxBUF register is
transmitted synchronously on the SDO (output) pin
while synchronous data is received from the Master
device on the SDI (input) pin. In this mode, the Master
device controls the synchronous data transfer with the
SCK clock pin by generating 8, 16 or 32 clock pulses,
depending on the selected data size.
17.2.3.1
The SDO pin is an output and the SPI pin is an input.
Setting the control bit, DISSDO (SPIxCON<12>),
disables transmission at the SDO pin if Receive Only
mode of operation is desired.
Refer to Table 17-7.
The SDI (input) must be configured to properly sample
the data received from the slave device by configuring
the sample bit, SMP (SPIxCON<9>).
Refer to timing diagram shown in Figure 17-4 to deter-
mine the appropriate settings.
Data transfers can be 8, 16, or 32 bits and are
configured
(SPIxCON<11:10>).
Refer to Section 17.2.1 “8, 16, 32-Bit Operation” for
details.
Slave Select Synchronization: The SSx pin allows a
Synchronous Slave mode. If the SSEN (SPIxCON<7>)
bit is set, transmission and reception is enabled in
Slave mode only if the SSx pin is driven to a low state.
If the SSEN bit is not set, the SSx pin does not affect
the module operation in Slave mode.
17.2.3.2
The following bits must be configured as shown for the
Slave mode of operation when configuring the
SPIxCON register:
• Enable Slave Mode –
• Disable Framed SPI support – FRMEN
The remaining bits are shown with example configura-
tions and may be configured as desired:
• Enable module control of SDO pin –
• Configure SCK clock polarity to Idle high –
• Configure SCK clock edge transition from Idle to
• Disable Slave Select Pin –
• Select 16-bit data width –
• Sample data input at middle –
DS61143C-page 386
(SPIxCON<31>) = 0
active – CKE (SPIxCON<8>) = 0
MSTEN (SPIxCON<5>) = 0.
DISSDO (SPIxCON<12>) = 0
CKP (SPIxCON<6>) = 1
SSEN (SPIxCON<7>) = 0
MODE<32,16> (SPIxCON<11:10>) = 01
SMP (SPIxCON<9>) = 0
SLAVE MODE
Slave Mode Operations
using
Slave SPIxCON Configuration
control
bits.
MODE<32,16>
Preliminary
• Enable SPI module when CPU Idle –
17.2.3.3
The following steps are used to set up the SPI module
for the Slave mode of operation:
1.
2.
3.
1.
2.
3.
4.
5.
SIDL (SPIxCON<13>) = 0
Note 1: The user must turn off the SPI device
If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
Stop and reset the SPI module by clearing the
ON bit.
Clear the receive buffer.
If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
• Set the SPIx interrupt enable bits in the
• Write the SPIx interrupt priority and subprior-
Clear the SPIROV bit (SPIxSTAT<6>).
Write the selected configuration settings to the
SPIxCON
(<SPIxCON<5>) = 0.
Enable SPI operation by setting the ON bit
(SPIxCON<15>).
Transmission (and reception) will start as soon
as the master provides the serial clock.
respective IFS0/1 register.
respective IEC0/1 register.
ity bits in the respective IPC5/7 register.
2: The SPI device must be turned off prior to
3: The SPIxSR register cannot be written
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
changing the mode from Master to Slave.
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
Slave Mode Initialization
register
© 2008 Microchip Technology Inc.
with
MSTEN