PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 403

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard. Figure 18-1 shows the I
diagram.
The PIC32MX3XX/4XX devices have up to two I
interface modules, denoted as I2C1 and I2C2. Each
I
and the SDAx pin is data.
Each I
key features:
• I
• I
• I
• I
• Serial Clock Synchronization for I
• I
• Provides Support for Address Bit Masking.
18.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “PIC32MX3XX/4XX
Reference Manual” (DS61132).
© 2008 Microchip Technology Inc.
2
C module has a 2-pin interface: the SCLx pin is clock
Note:
Operation.
Master and Slaves.
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
Collision and Arbitrates Accordingly.
2
2
2
2
2
2
2
C Interface Supporting both Master and Slave
C Slave Mode Supports 7 and 10-Bit Address.
C Master Mode Supports 7 and 10-Bit Address.
C Port allows Bidirectional Transfers between
C Supports Multi-master Operation; Detects Bus
C Slave Operation with 7 or 10-Bit Address
C Master Operation with 7 or 10-Bit Address
2
2
C module can operate either as a slave or a
C module ‘I2Cx’ (x = 1 or 2) offers the following
INTER-INTEGRATED CIRCUIT
(I
Operating Modes
2
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
C™)
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
2
C serial communication
2
C) module provides
2
2
C Port can be
C module block
Preliminary
2
C
18.2
The I2CxCON register allows control of the module’s
operation. The I2CxCON register is readable and writ-
able. I2CxSTAT register contains status flags indicating
the module’s state during operation.
I2CxRCV is the receive register. When the incoming
data is shifted completely, it is moved to the I2CxRCV
register. I2CxTRN is the transmit register to which
bytes are written during a transmit operation.
The I2CxADD register holds the slave address. A
Status bit, ADD10, indicates 10-Bit Addressing mode.
The I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated. The I2CxRSR shift
register is not directly accessable to the programmer.
18.3
The I
Slave Interrupt (I2CxSIF), Master Interrupt (I2CxMIF)
and Bus Collision Interrupt (I2CxBIF).
18.4
In I
Generator (BRG) resides in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to ‘0’ and stops until another reload has
taken place. If clock arbitration is taking place, for
instance, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 18-1:
PBCLK is the peripheral clock speed. FSCL is the
desired I
2
C Master mode, the reload value for the Baud Rate
2
C module generates three interrupt signals:
PIC32MX3XX/4XX
I2C
2
I
I
Baud Rate Generator
C bus speed.
2
2
C Registers
C Interrupts
x
2
BRG =
C standard, F
[
SERIAL CLOCK RATE
FSCL x 2
PBCLK
SCL
may be 100 kHz or
DS61143C-page 401
]
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