PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 88

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
5.2
The PIC32MX3XX/4XX internal device Reset signal is
SYSRST and can be generated from multiple Reset
sources, such as POR (Power-on Reset), BOR
(Brown-out Reset), MCLR (Master Clear Reset),
WDTO (Watchdog Time-out Reset), SWR (Software
Reset) and CMR (Configuration Mismatch Reset). A
Reset source sets a corresponding status bit in the
RCON register to indicate the type of Reset (see
Register 5-1). A system Reset is active at first the POR
and asserted until device configuration settings are
loaded and the clock oscillator sources become stable.
The system Reset is then deasserted allowing the CPU
to start fetching code after 8 system clock cycles (SYS-
CLK).
5.2.1
A power-on event generates an internal Power-on
Reset pulse when a V
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR pulse. In particular, V
must fall below V
more information on the V
fications, refer to Section 30.0 “Electrical Character-
istics” of this device family data sheet.
5.2.2
Whenever the MCLR pin is driven low, the device asyn-
chronously asserts SYSRST provided the input pulse on
MCLR is longer than a certain minimum width, as spec-
ified in Section 30.0 “Electrical Characteristics” of
this device family data sheet.
MCLR provides a filter to minimize the effects of noise
and to avoid unwanted Reset conditions. The EXTR bit
(RCON<7>) is set to indicate the MCLR Reset.
EXAMPLE 5-1:
DS61143C-page 86
/* The following code illustrates a software Reset */
// assume interrupts are disabled
// assume the DMA controller is suspended
// assume the device is locked
/* perform a system unlock sequence */
// starting critical sequence
SYSKEY = 0xaa996655; //write first unlock key to SYSKEY
SYSKEY = 0x556699aa
/* set SWRST bit to arm reset */
RSWRSTSET = 1;
/* read RSWRST register to trigger reset */
unsigned int dummy;
dummy = RSWRST;
/* prevent any unwanted code execution until reset occurs*/
while(1);
Reset Modes
POWER-ON RESET (POR)
MCLR RESET (EXTR)
POR
before a new POR is initiated. For
DD
SOFTWARE RESET COMMAND SEQUENCE
rise is detected above V
POR
//write second unlock key to SYSKEY
and V
DD
rise rate speci-
POR
Preliminary
DD
.
5.2.3
The PIC32MX3XX/4XX CPU core doesn’t provide a
specific RESET “instruction”; however, a hardware
Reset can be performed in software (Software Reset)
by executing a Software Reset command sequence:
• Write the system unlock sequence
• Set bit, SWRST (RSWRST<0>) = 1
• Read RSWRST register – Reset occurs
• Follow with “while(1);” or 4 “NOP” instructions
Writing a ‘1’ to the RSWRST register sets bit SWRST,
arming the Software Reset. The subsequent read of
the RSWRST register triggers the Software Reset,
which should occur on the next clock cycle following
the read operation. To ensure no other user code is
executed before the Reset event occurs, it is recom-
mended that 4 ‘NOP’ instructions or a “while(1);” state-
ment be placed after the READ instruction.
The SWR Status bit (RCON<6>) is set to indicate the
Software Reset.
SOFTWARE RESET (SWR)
© 2008 Microchip Technology Inc.