PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 500

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
22.3.9
The Buffer Fill mode allows the output buffer to be used
as a single, 16-word buffer or two, 8-word buffers.
When BUFM is ‘0’, the complete 16-word buffer is used
for all conversion sequences. Conversion results will
be written sequentially in the buffer, starting at
ADC1BUF0 until the number of samples as defined by
SMPI<3:0> (AD1CON2<5:2>) is reached. The next
conversion result will be written to ADC1BUF0 and the
process repeats. If the ADC interrupt is enabled, an
interrupt will be generated when the number of
samples in the buffer equals SMPI<3:0>.
When the BUFM bit (AD1CON2<1>) is ‘1’, the 16-word
results buffer (ADRES) will be split into two 8-word
groups. Conversion results will be written sequentially
into the first buffer starting at ADC1BUF0, BUFS
(AD1CON2<7>) will be cleared, until the number of
samples as defined by SMPI<3:0> (AD1CON2<5:2>)
is reached. The ADC interrupt flag will then be set.
After the ADC interrupt flag is set, the following result
will be written sequentially to the second buffer, starting
at ADC1BUF8 The next conversion result will be writ-
ten to the second buffer; starting at ADC1BUF8, BUFS
(AD1CON2<7>) will be set until the number of samples
as defined by SMPI<3:0> (AD1CON2<5:2>) is
reached. The ADC interrupt flag will then be set.
The process then restarts with BUFS = 0 and the
results being written to the first buffer.
22.3.10
The ADC has two input MUXs that connect to the SHA.
These MUXs are used to select which analog input is
to be sampled. Each of the MUXs have a positive and
a negative input.
22.3.10.1
The user may select one of up to 16 analog inputs, as
determined by the number of analog channels on the
device, as the positive input of the SHA. The
CH0SA<3:0> bits (AD1CHS<19:16>) select the posi-
tive analog input.
The user may select either V
input. The CH0NA bit (AD1CHS<23>) selects the ana-
log input for the negative input of channel 0. Using AN1
as the negative input allows unipolar differential mea-
surements.
The ALTS bit (AD1CON2<0>) must be clear for this
mode of operation.
DS61143C-page 498
BUFFER FILL MODE
SELECTING THE MUX TO BE
CONNECTED TO THE ADC
(ALTERNATING SAMPLE MODE)
Single Input Selection
R
- or AN1 as the negative
Preliminary
22.3.10.2
The ALTS bit causes the module to alternate between
the two input MUXs.
The inputs specified by CH0SA<3:0> and CH0NA are
called the MUX A inputs. The inputs specified by
CH0SB<3:0> and CH0NB are called the MUX B inputs.
When ALTS is ‘1’, the module will alternate between
the MUX A inputs on one sample and the MUX B inputs
on the subsequent sample. When ALTS is ‘0’, only the
inputs specified by CH0SA<3:0> and CH0NA are
selected for sampling.
22.3.11
The ADC module can use the internal RC oscillator or
the PBCLK as the conversion clock source.
When the internal RC oscillator is used as the clock
source, ADRC (AD1CON3<15>) = 1, the T
period of the oscillator, no prescaler are used. When
using the internal oscillator the ADC can continue to
function in SLEEP and in IDLE.
When the PBCLK is used as the conversion clock
source, ADRC = 0, the T
after the prescaler ADCS<7:0> (AD1CON3<7:0>) is
applied.
The A/D converter has a maximum rate at which con-
versions may be completed. An analog module clock,
T
sion requires 12 clock periods (12 T
The period of the ADC conversion clock is software
selected using a 8-bit counter. There are 256 possible
options for T
(AD1CON3<7:0>).
Equation 22-3 gives the T
ADCS control bits and the device instruction cycle
clock period, T
EQUATION 22-3:
For correct A/D conversions, the ADC conversion clock
(T
AD
AD
, controls the conversion timing. The A/D conver-
) must be selected to meet the minimum T
SELECTING THE ADC
CONVERSION CLOCK SOURCE
AND PRESCALER
ADCS = (T
T
Alternating Input Selections
AD
AD
CY
, specified by the ADCS<7:0> bits
.
= 2 • (T
ADC CONVERSION
CLOCK PERIOD
© 2008 Microchip Technology Inc.
AD
AD
PB
AD
/(2 •T
is the period of the PBCLK
(AADCS + 1)
value as a function of the
PB
)) - 1
AD
).
AD
AD
is the
time.