PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 576

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
28.2.4.3
The Instruction Shift register is a 5-bit shift register
used for selecting the actions to be performed and/or
what data registers to be accessed. Instructions are
shifted in, Least Significant bit first, and then decoded.
A list and description of implemented instructions is
given in Section 28.2.4.6 “JTAG Instructions”.
28.2.4.4
Once an instruction is shifted in and updated into the
Instruction Register, the TAP controller places certain
data registers between the TDI and TDO pins. Addi-
tional data values can then be shifted into these data
registers as needed.
The PIC32MX3XX/4XX device supports three data
registers:
• BYPASS Register: A single bit register which
• DEVID Register: A 32-bit part identifier. It consists
• MCHP Command Shift Register: An 8-bit Shift
TABLE 28-3:
TABLE 28-4:
DS61143B-page 574
Opcode
Opcode
allows the boundary scan test data to pass
through the selected device to adjacent devices.
The BYPASS register is placed between the TDI
and TDO pins when the BYPASS instruction is
active.
of an 11-bit manufacturer ID assigned by the IEEE
(29h for Microchip Technology), device part num-
ber and device revision identifier. When the
IDCODE instruction is active, the device ID regis-
ter is placed between the TDI and TDO pins. The
device data ID is then shifted out on to the TDO
pin, on the next 32 falling edges of TCK, after the
TAP controller is in the Shift_DR.
register that is placed between the TDI and TDO
pins when the MCHP_CMD instruction is active.
This Shift register is used to shift in Microchip
commands.
0x1F
0x00
0x01
0x02
0x06
0x01
0x07
0x04
Bypass
HIGHZ
ID Code
Sample/Preload
EXTEST
MTAP_IDCODE
MTAP_COMMAND
MTAP_SW_MTAP
Instruction Shift Register and
Instruction Register
Data Registers
JTAG COMMANDS
MICROCHIP TAP IR COMMANDS
Name
Name
Bypasses device in test chain
Places device in a high-impedance state, all pins are forced to inputs
Shifts out the device’s ID code
Samples all pins or loads a specific value into output latch
Boundary scan
Shifts out the device’s ID code
Configures Microchip TAP controller for DR commands
Selects Microchip TAP controller
Preliminary
28.2.4.5
The BSR is a large Shift register that is comprised of all
the I/O Boundary Scan Cells (BSCs), daisy-chained
together. Each I/O pin has one BSC, each containing 3
BSC registers, an input cell, an output cell and a control
cell. When the SAMPLE/PRELOAD or EXTEST instruc-
tions are active, the BSR is placed between the TDI
and TDO pins, with the TDI pin as the input and the
TDO pin as the output.
The size of the BSR depends on the number of I/O pins
on the device. For example, the 100-pin PIC32MX gen-
eral purpose parts have 82 I/O pins. With 3 BSC regis-
ters for each of the 82 I/Os, this yields a Boundary Scan
register length of 244 bits. This is due to the MCLR pin
being an input only BSR cell. Information on the I/O
port pin count of other PIC32MX3XX/4XX devices can
be found in their specific device data sheets.
28.2.4.6
PIC32MX3XX/4XX devices support the mandatory
instruction set specified by IEEE 1149.1, as well as sev-
eral optional public instructions defined in the specifica-
tion. These devices also implement instructions that
are specific to Microchip devices.
The mandatory JTAG instructions are:
• BYPASS (0x1F): Used for bypassing a device in a
• SAMPLE/PRELOAD (0x02): Captures the I/O
• EXTEST (0x06): Allows the external circuitry and
Microchip has implemented optional JTAG instructions
and
PIC32MX3XX/4XX devices. Please refer to Table 28-3,
Table 28-4, Table 28-5 and Table 28-6.
test chain; this allows the testing of off-chip
circuitry and board level interconnections.
states of the component, providing a snapshot of
its operation.
interconnections to be tested, by either forcing
various test patterns on the output pins, or
capturing test results from the input pins.
Device Integration
Device Integration
manufacturer-specific
Boundary Scan Register (BSR)
JTAG Instructions
© 2008 Microchip Technology Inc.
JTAG
commands
in