PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 358

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
15.1
The input capture module can select between one of
two 16-bit timers for the time base, or two 16-bit timers
together to form a 32-bit timer. Setting ICTMR
(ICxCON<7>) to ‘0’ selects the Timer3 for capture.
Setting ICTMR (ICxCON<7>) to 1 selects the Timer2
for capture.
An input capture channel configured to support 32-bit
capture, may use a 32-bit timer resource for capture.
By setting ICC32 (ICxCON<8>) to ‘1’, a 32-bit timer
resource is captured. The 32-bit timer resource is
routed into the module using the existing 16-bit timer
inputs.
The timers clock can be setup using the internal periph-
eral clock source, or using a synchronized external
clock source applied at the TxCK pin.
FIGURE 15-2:
15.3
In Prescaled Capture Event mode, the input capture
module triggers a capture event on either every fourth
or every sixteenth rising edge. These modes are
selected by setting the ICM (ICxCON<2:0>) bits to
‘100’ or ‘101’, respectively.
DS61143C-page 356
Synchronized Capture
Timer Selection
Prescaled Capture Event Modes
Capture Interrupt
Peripheral Clock
Capture Data
Timer Count
ICx Input
SIMPLE CAPTURE EVENT TIMING DIAGRAM CAPTURE EVERY RISING EDGE
n
n+1
Preliminary
n+2
m
15.2
These modes are specified by setting the ICM
(ICxCON<2:0>) bits to ‘010’, ‘011’, or ‘110’. Setting
ICM = ‘011’ configures the module to capture the timer
value on any rising edge of the capture input. ICM =
‘010’ configures the module to capture the timer on any
falling edge of the capture input. Setting ICM = ‘110’
configures the channel to capture the timer on every
transition of the capture input, beginning with the edge
specified by ICFEDGE (ICxCON<9>). In Simple Cap-
ture Event mode, the prescaler is not used. See
Figure 15-2 for simplified timing diagrams of a simple
capture event.
An input capture interrupt event is generated after one,
two, three or four timer count captures, as configured
by ICI (ICxCON<6:5>).
Note: Since the capture input must be synchro-
Note: Since the capture input must be synchro-
m+1
Simple Capture Event Modes
nized to the peripheral clock, the module
captures the timer count value, which is valid
2-3 peripheral clock cycles (T
capture event.
nized to the peripheral clock, the timer count
value is captured, which is valid 2-3
peripheral clock periods after the capture
event.
n + 2
m+2
© 2008 Microchip Technology Inc.
m+3
m+4
m + 3
PB
m+5
) after the