PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
10.4
The Pattern Match mode is enabled by setting the
PATEN bit (DCHxECON<5>).
This feature is useful in applications where a variable
data size is required and eases the setup of the DMA
channel. A good usage is for transferring ASCII com-
mand strings from an UART, <CR> ended. This is also
useful for implementing string copy routines with DMA
support.
Pattern Match mode features:
• Allows the user to end a transfer if a byte of data
• A pattern match is treated the same way as a
• The pattern is stored in the DCHxDAT register.
• If any byte in the source matches DCHxDAT, a
10.4.1
The Pattern Match mode is an option for use when
performing DMA transfers in basic DMA configuration.
Therefore, the steps needed in Pattern Match mode
are identical to those used in basic DMA configuration.
An extra step is needed to store the desired pattern in
DCHxDAT register.
The following steps are recommended to be taken to
configure a DMA transfer in Pattern Match mode:
• Disable the DMA channel interrupts in the INT
• Clear any existing channel interrupt flags in the
• Enable the DMA controller (if not already
• Set Channel Control register: Priority,
• Set the channel event control: clear/set the events
• Set the pattern in the DCHxDAT register.
• Set the transfer source and destination physical
• Set the source and destination sizes (DCHxSSIZ,
• Set the cell transfer size (DCHxCSIZ).
• Clear any existing event flag in DCHxINT register.
DS61143C-page 230
written during a transaction matches a specific
pattern.
block transfer complete, where the CHBCIF
(DCHxINT<3>) bit is set and the CHEN
(DCHxCON<7>) bit is cleared provided
auto-enable CHAEN = 0 (DCHxCON<4>).
pattern match is detected.
controller.
INT controller.
enabled) in DMACON register.
Auto-Enable mode, etc., in DCHxCON. Don’t
enable the channel yet.
starting and aborting the transfer. Set the pattern
match enable PATEN in DCHxECON.
addresses (DCHxSSA and DCHxDSA registers).
DCHxDSIZ registers).
Pattern Match Termination
PATTERN MATCH MODE
CONFIGURATION
Preliminary
• If using interrupts:
• Enable the selected DMA channel with CHEN
• If not using system events to start the DMA
• Until the DMA transfer is complete, you can do
• If you enabled transfer complete interrupts (cell
• Otherwise, you can poll the DMA channel to see if
Refer to Example 10-2.
- Set the conditions that will generate an inter-
- Set the DMA channel interrupt priority and
- Enable the DMA channel interrupt in the INT
(DCHxCON<7>).
transfer use CFORCE (DCHxECON<7>) to start
transfer.
some other processing.
complete, block complete, etc) you’ll be notified in
the ISR that the DMA transfer completed.
the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
rupt in the DCHxINT register (at least error
interrupt enable and abort interrupt enable,
usually block complete interrupt).
subpriority in the INT controller.
controller.
© 2008 Microchip Technology Inc.