PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 201

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-3:
TABLE 10-4:
© 2008 Microchip Technology Inc.
Note
BF88_303C DCRCCONINV
BF88_304C DCRCDATAINV
BF88_305C DCRCXORINV
Address
BF88_306C
BF88_307C DCH0ECONINV
BF88_308C
BF88_309C
BF88_3030
BF88_3034 DCRCCONCLR
BF88_3038 DCRCCONSET
BF88_3040
BF88_3044 DCRCDATACLR 31:0
BF88_3048 DCRCDATASET 31:0
BF88_3050
BF88_3054 DCRCXORCLR
BF88_3058 DCRCXORSET
BF88_3060
BF88_3064 DCH0CONCLR
BF88_3068
BF88_3070
BF88_3074 DCH0ECONCLR 31:0
BF88_3078 DCH0ECONSET 31:0
BF88_3080
BF88_3084
BF88_3088
BF88_3090
BF88_3094
BF88_3098
Address
Virtual
Virtual
1:
(1)
The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n.
DCH0CONSET
DCH0CONINV
DCH0SSACLR
DCH0SSASET
DCH0INTCLR
DCH0INTSET
DCH0SSAINV
DCH0INTINV
DCRCDATA
DCH0ECON
DCRCCON
DCRCXOR
DCH0CON
DCH0SSA
DCH0INT
DMA CRC SFR SUMMARY
DMA CHANNEL 0 SFR SUMMARY
Name
Name
31:24
23:16
31:24
23:16
31:24
23:16
15:8
31:0
31:0
31:0
15:8
31:0
15:8
31:0
31:0
31:0
31:24
23:16
31:24
23:16
31:24
23:16
31:24
23:16
7:0
7:0
7:0
15:8
31:0
31:0
31:0
15:8
31:0
15:8
31:0
31:0
31:0
15:8
31:0
31:0
31:0
7:0
7:0
7:0
7:0
31/23/15/7
31/23/15/7
CRCEN
CFORCE
CHSDIE
CHSDIF
CHEN
Bit
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
30/22/14/6
CRCAPP
30/22/14/6
CABORT
CHSHIE
CHSHIF
CHAED
Bit
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
Write inverts selected bits in DCRCDATA, read yields undefined value
Write clears selected bits in DCRCDATA, read yields undefined value
Write inverts selected bits in DCRCCON, read yields undefined value
Write inverts selected bits in DCRCXOR, read yields undefined value
Write inverts selected bits in DCH0ECON, read yields undefined value
Write clears selected bits in DCRCCON, read yields undefined value
Write clears selected bits in DCRCXOR, read yields undefined value
Write clears selected bits in DCH0ECON, read yields undefined value
Write inverts selected bits in DCH0CON, read yields undefined value
Write sets selected bits in DCRCDATA, read yields undefined value
Write clears selected bits in DCH0CON, read yields undefined value
Write inverts selected bits in DCH0SSA, read yields undefined value
Write sets selected bits in DCRCCON, read yields undefined value
Write sets selected bits in DCRCXOR, read yields undefined value
Write sets selected bits in DCH0ECON, read yields undefined value
Write clears selected bits in DCH0SSA, read yields undefined value
Write inverts selected bits in DCH0INT, read yields undefined value
Write clears selected bits in DCH0INT, read yields undefined value
Write sets selected bits in DCH0CON, read yields undefined value
Write sets selected bits in DCH0SSA, read yields undefined value
Write sets selected bits in DCH0INT, read yields undefined value
Preliminary
29/21/13/5
29/21/13/5
CHDDIE
CHDDIF
CHCHN
PATEN
Bit
—
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
28/20/12/4
28/20/12/4
SIRQEN
CHDHIE
CHDHIF
CHAEN
DCRCDATA<15:8>
DCRCXOR<15:8>
DCRCDATA<7:0>
Bit
DCRCXOR<7:0>
—
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
CHSSA<31:24>
CHSSA<23:16>
CHAIRQ<7:0>
CHSIRQ<7:0>
CHSSA<15:8>
CHSSA<7:0>
PIC32MX3XX/4XX
27/19/11/3
27/19/11/3
AIRQEN
CHBCIE
CHBCIF
Bit
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
—
26/18/10/2
26/18/10/2
CHEDET
CHCCIE
CHCCIF
Bit
—
—
—
—
—
—
—
Bit
—
—
—
—
—
—
—
PLEN<3:0>
25/17/9/1
25/17/9/1
CHTAIE
DS61143C-page 199
CHTAIF
Bit
—
—
—
—
—
—
Bit
—
—
—
—
—
—
—
CRCCH<1:0>
CHPRI<1:0>
24/16/8/0
24/16/8/0
CHCHNS
CHERIE
CHERIF
Bit
—
—
—
—
—
—
Bit
—
—
—
—
—
—