PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 200

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
FIGURE 10-1:
10.1
TABLE 10-2:
DS61143C-page 198
BF88_300C
BF88_3000
BF88_3004
BF88_3008
BF88_3010
BF88_3020
Address
Virtual
INT Controller
Peripheral Bus
DMA Controller Registers
DMACONCLR
DMACONSET
DMACONINV
DMAADDR
DMASTAT
DMACON
DMA GLOBAL SFR SUMMARY
Name
Address Decoder
DMA CONTROLLER BLOCK DIAGRAM
Global Control
(DMACON)
31:24
23:16
31:24
23:16
31:24
23:16
15:8
31:0
31:0
31:0
15:8
15:8
7:0
7:0
7:0
System IRQ
31/23/15/7
ON
Bit
—
—
—
—
—
—
—
30/22/14/6
FRZ
Bit
—
—
—
—
—
—
—
Write inverts selected bits in DMACON, read yields undefined value
Write clears selected bits in DMACON, read yields undefined value
Channel n Control
Channel 0 Control
Channel 1 Control
Write sets selected bits in DMACON, read yields undefined value
Preliminary
29/21/13/5
SIDL
Bit
—
—
—
—
—
—
—
SUSPEND
28/20/12/4
Channel Priority
DMAADDR<31:24>
DMAADDR<23:16>
DMAADDR<15:8>
Arbitration
DMAADDR<7:0>
Bit
—
—
—
—
—
—
—
I
I
I
I
0
2
1
n
Y
27/19/11/3
RDWR
Bit
—
—
—
—
—
—
—
Bus Interface
26/18/10/2
© 2008 Microchip Technology Inc.
Bit
—
—
—
—
—
—
—
—
Device Bus + Bus Arbitration
25/17/9/1
Bit
—
—
—
—
—
—
DMACH<1:0>
24/16/8/0
Bit
—
—
—
—
—
—
—