PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 229

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2
A DMA channel will transfer data from a source to a
destination without CPU intervention.
DMA controller configuration resources:
• The DMA Controller and the corresponding DMA
• The source and destination of the transfer are
• The source and destination are further indepen-
• A DMA transfer can be initiated in one of two
• At each event requiring a DMA transfer, a num-
• The channel keeps track of the number of bytes
• The Source and Destination Pointers are read-
• Interrupts are generated when the Source or
© 2008 Microchip Technology Inc.
channel have to be enabled using the ON
(DMACON<15>) and the CHEN (DCHxCON<7>)
bits.
programmable using the DCHxSSA and
DCHxDSA registers respectively.
dently configurable using the DCHxSSIZ and
DCHxDSIZ registers.
ways:
- Software can initiate a transfer by setting the
- An interrupt event occurs that matches the
Note:
ber of bytes specified by the cell size (DCHxCSIZ)
will be transferred (one or more transactions will
occur).
transferred from the source to destination, using
Source and Destination Pointers (DCHxSPTR
and DCHxDPTR).
only and are updated after every transaction.
Destination pointer is half of the source or desti-
nation size (DCHxSSIZ/2 or DCHxDSIZ/2), or
when the source or destination counter equals the
size of the source or destination. These interrupts
are CHSHIF, CHDHIF and CHSDIF, CHDDIF,
respectively.
channel CFORCE (DCHxECON<7>) bit.
CHSIRQ (DCHxECON<15:8>) interrupt and
SIRQEN = 1 (DCHxECON<4>). The user can
select any interrupt on the device to start a
DMA transfer.
DMA Controller Operation
experience heavy bus load.
BMX arbitration mode 2 (rotating priority) is
recommended
when
a
system
may
Preliminary
• The Source and Destination Pointers are reset:
• Normally, the DMA channel remains enabled until
• When the channel is disabled, further transfers
• A DMA transfer request will be stopped/aborted
• When a channel abort interrupt occurs, the
- On any device Reset.
- When the DMA is turned off (ON bit
Note:
- A block transfer completes (regardless of the
- A pattern match terminates a transfer
- CABORT (DCHxECON<6>) flag is written.
Note:
- If the channel source address (DCHxSSA) is
- Similarly, updates to the Destination Address
the DMA channel has completed a block transfer
unless the auto-enable feature is turned on
(i.e., CHAEN = 1).
will be prohibited until the channel is re-enabled
(CHEN is set to ‘1’).
by:
- Writing the CABORT bit (DCHxECON<6>).
- Pattern match occurs if pattern match is
- Interrupt event occurs on the device that
- An address error is detected.
- A block transfer completes provided that
Channel Abort Interrupt Flag, CHTAIF,
(DCHxINT<1>) is set. This allows the user to
detect and recover from an aborted DMA transfer.
When a transfer is aborted, any transaction
currently underway will be completed.
(DMACON<15>) is ‘0’).
state of CHAEN (DCHxCON<4>)).
(regardless of the state of auto-enable
CHAEN (DCHxCON<4>)).
updated, the Source Pointer (DCHxSPTR)
will be reset.
(DCHxDSA) will cause the Destination
Pointer (DCHxDPTR) to be reset.
enabled PATEN = 1 (DCHxECON<5>), pro-
vided that channel CHAEN is not set.
matches the CHAIRQ (DCHxECON<23:16>)
interrupt if enabled by AIRQEN
(DCHxECON<3>).
Channel Auto-Enable mode (CHAEN) is not
set.
PIC32MX3XX/4XX
Always wait for the channels to complete
the current transactions (or abort first and
make sure the transfers were successfully
aborted)
controller OFF.
If the DMA channel is suspended in the mid-
dle of a transfer (If CHEN (DCHxCON)<7>
= 0) or if the DMA controller is suspended in
the middle of a transfer (If SUSPEND
(DMACON)<12> = 1) and a CABORT is
issued, the Source, Destination and Cell
pointers are not Reset.
before
switching
DS61143C-page 227
the
DMA