ATMEGA1280V-8AU Atmel, ATMEGA1280V-8AU Datasheet - Page 286
ATMEGA1280V-8AU
Manufacturer Part Number
ATMEGA1280V-8AU
Description
IC MCU AVR 128K FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1280V-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Controller Family/series
AVR MEGA
No. Of I/o's
86
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA1280V-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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25.6.3
25.6.4
2549M–AVR–09/10
Offset Compensation Schemes
ADC Accuracy Definitions
The stage has a built-in offset cancellation circuitry that nulls the offset of differential measure-
ments as much as possible. The remaining offset in the analog path can be measured directly by
selecting the same channel for both differential inputs. This offset residue can be then sub-
tracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
•
Figure 25-11. Offset Error
•
Figure 25-12. Gain Error
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB.
Output Code
Output Code
Offset
Error
ATmega640/1280/1281/2560/2561
Gain
Error
V
V
REF
REF
Input Voltage
Input Voltage
Ideal ADC
Actual ADC
n
Ideal ADC
Actual ADC
-1.
REF
in 2
n
steps
286
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