AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 835

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.8
43.9
43.9.1
6289C–ATARM–28-May-09
Conversion Triggers
Operating Modes
ADC Mode
Conversions of the active analog channels are started with a software or a hardware trigger.
The software trigger is provided by writing the
1.
The hardware trigger can be selected by the filed TRGMOD in the TSADCC Trigger Register
(TSADCC_TRGR) between:
Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hard-
ware trigger is selected, the start of a conversion can still be initiated by the software trigger.
The Touch Screen ADC Controller features several operating modes, each defining a conver-
sion sequence:
The Operating Mode of the TSADCC is programmed in the field TSAMOD in the
Mode
The conversion sequences for each Operating Mode are described in the following paragraphs.
The conversion sequencer, combined with the Sleep Modes, allows automatic processing with
minimum processor intervention and optimized power consumption. In any case, the sequence
starts with a trigger event.
Note:
In the ADC Mode, the active channels are defined by the
which is defined by writing the
able
the
possible.
At each trigger, the following sequence is performed:
• an edge, either rising or falling or any, detected on the external trigger pin TSADTRG
• the Pen Detect, depending on how the PENDET bit is set in the
• a continuous trigger, meaning the TSADCC restarts the next sequence as soon as it finishes
• a periodic trigger, which is defined by programming the field TRGPER in the
• The ADC Mode: at each trigger, all the enabled channels are converted
• The Touch Screen Mode: at each trigger, the touch screen inputs are converted with the
4. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
5. If Channel 0 is enabled, convert Channel 0 and store result in both TSADCC_CDR0
6. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1
the current one, in this case, only one software trigger is required at the beginning
Trigger Register”
switches accordingly set and the results are processed and stored in the corresponding data
registers
“TSADCC Last Converted Data
Register”. The results are stored in the
and TSADCC_LCDR.
and TSADCC_LCDR.
Register”.
The reference voltage pins always remain connected in normal mode as in sleep mode.
“TSADCC Channel Enable Register”
AT91SAM9R64/RL64 Preliminary
Register”, so that data transfers by using the PDC are
“TSADCC Channel Data Register x (x = 0..5)”
“TSADCC Control Register”
“TSADCC Channel Status
“TSADCC Mode Register”
and
“TSADCC Channel Dis-
with the bit START at
“TSADCC
“TSADCC
Register”,
and in
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