ATMEGA128L-8AU Atmel, ATMEGA128L-8AU Datasheet - Page 91

IC AVR MCU 128K 8MHZ 3V 64TQFP

ATMEGA128L-8AU

Manufacturer Part Number
ATMEGA128L-8AU
Description
IC AVR MCU 128K 8MHZ 3V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128L-8AU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
2-Wire/JTAG/USART
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
4K Bytes
Input Output
53
Interface
2-Wire/JTAG/SPI/USART
Memory Type
Flash
Number Of Bits
8
Programmable Memory
128K Bytes
Timers
2-8-bit, 2-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128L-8AU
Manufacturer:
MURATA
Quantity:
120 000
Part Number:
ATMEGA128L-8AU
Manufacturer:
ATM
Quantity:
450
Part Number:
ATMEGA128L-8AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA128L-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA128L-8AU
Quantity:
7
Company:
Part Number:
ATMEGA128L-8AU
Quantity:
12 399
Company:
Part Number:
ATMEGA128L-8AU
Quantity:
74
Part Number:
ATMEGA128L-8AUR
Manufacturer:
Atmel
Quantity:
10 000
External Interrupt
Mask Register –
EIMSK
External Interrupt Flag
Register – EIFR
2467V–AVR–02/11
• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-
rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger
an interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep
mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF3:0 flags. See
Enable and Sleep Modes” on page 69
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
INTF7
INT7
R/W
R/W
7
0
7
0
INTF6
INT6
R/W
R/W
6
0
6
0
INTF5
INT5
R/W
R/W
5
0
5
0
for more information.
INTF4
INT4
R/W
R/W
4
0
4
0
INTF3
INT3
R/W
R/W
3
0
3
0
INTF2
INT2
R/W
R/W
2
0
2
0
INTF1
INT1
R/W
R/W
1
0
1
0
IINTF0
IINT0
R/W
R/W
ATmega128
0
0
0
0
EIMSK
EIFR
“Digital Input
91

Related parts for ATMEGA128L-8AU