DSPIC30F6010-20I/PF Microchip Technology, DSPIC30F6010-20I/PF Datasheet - Page 106
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DSPIC30F6010-20I/PF
Manufacturer Part Number
DSPIC30F6010-20I/PF
Description
IC PSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6010A-30IPF.pdf
(22 pages)
2.DSPIC30F6010-20IPF.pdf
(222 pages)
3.DSPIC30F6010-20IPF.pdf
(30 pages)
Specifications of DSPIC30F6010-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601020IPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6010-20I/PF
Manufacturer:
MICROCHI
Quantity:
20 000
dsPIC30F6010
EQUATION 17-1:
17.12.4
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit, or Restart/Stop condition. When the SCL pin
is allowed to float high, the Baud Rate Generator is
suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the
Baud Rate Generator is reloaded with the contents of
I2CBRG and begins counting. This ensures that the
SCL high time will always be at least one BRG rollover
count in the event that the clock is held low by an exter-
nal device.
17.12.5
Multi-Master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA, by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 1 and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The mas-
ter sets the MI2CIF pulse and resets the master portion
of the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are deasserted, and a
value can now be written to I2CTRN. When the user
services the I
tine, if the I
can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are deasserted,
and the respective control bits in the I2CCON register
are cleared to 0. When the user services the bus colli-
sion Interrupt Service Routine, and if the I
the user can resume communication by asserting a
Start condition.
DS70119E-page 104
2
I2CBRG
C port to its Idle state.
2
CLOCK ARBITRATION
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
C bus is free (i.e., the P bit is set) the user
2
C master event Interrupt Service Rou-
=
⎛
⎝
------------ -
F
F
SCL
SERIAL CLOCK RATE
CY
–
-------------------------- -
1 111 111
F
CY
⎞
⎠
2
–
C bus is free,
1
The Master continues to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit is
set.
A write to the I2CTRN starts the transmission of data at
the first data bit, regardless of where the transmitter left
off when bus collision occurred.
In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
17.13 I
17.13.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
clocks stop, the transmission is aborted. Similarly, if
Sleep occurs in the middle of a reception, the reception
is aborted.
17.13.2
For the I
or continues on Idle. If I2CSIDL = 0, the module contin-
ues operation on assertion of the Idle mode. If I2CSIDL
= 1, the module stops on Idle.
2
Sleep and Idle Modes
C, the I2CSIDL bit selects if the module stops
2
C Module Operation During CPU
I
SLEEP MODE
I
MODE
2
2
C OPERATION DURING CPU
C OPERATION DURING CPU IDLE
© 2006 Microchip Technology Inc.
2
C