DSPIC30F6010-20I/PF Microchip Technology, DSPIC30F6010-20I/PF Datasheet - Page 135
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F6010-20I/PF
Manufacturer Part Number
DSPIC30F6010-20I/PF
Description
IC PSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6010A-30IPF.pdf
(22 pages)
2.DSPIC30F6010-20IPF.pdf
(222 pages)
3.DSPIC30F6010-20IPF.pdf
(30 pages)
Specifications of DSPIC30F6010-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601020IPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6010-20I/PF
Manufacturer:
MICROCHI
Quantity:
20 000
• Write the SMPI<3:0> control bits in the ADCON2
• Configure the A/D clock period to be:
• Configure the sampling time to be 2 T
• Select at least two channels per analog input pin
20.7.2
The following configuration items are required to
achieve a 750 ksps conversion rate. This configuration
assumes that a single analog input is to be sampled.
• Comply with conditions provided in Table 20-2
• Connect external V
• Set SSRC<2:0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Enable one sample and hold channel by setting
• Write the SMPI<3:0> control bits in the ADCON2
• Configure the A/D clock period to be:
• Configure the sampling time to be 2 T
20.7.3
The configuration for 600 ksps operation is dependent
on whether a single input pin is to be sampled or
whether multiple pins will be sampled.
20.7.3.1
When performing conversions at 600 ksps for a single
analog input, at least two sample and hold channels
must be enabled. The analog input multiplexer must be
configured so that the same input pin is connected to
© 2006 Microchip Technology Inc.
ADCON2 register
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI<3:0> = 0001 since at least two sample and
hold channels should be enabled
by writing to the ADCS<5:0> control bits in the
ADCON3 register
writing: SAMC<4:0> = 00010
by writing to the ADCHS register
the recommended circuit shown in Figure 20-2
enable the auto-convert option
control bit in the ADCON1 register
CHPS<1:0> = 00 in the ADCON2 register
register for the desired number of conversions
between interrupts
by writing to the ADCS<5:0> control bits in the
ADCON3 register
writing: SAMC<4:0> = 00010
(12 + 2) X 750,000
750 ksps CONFIGURATION
GUIDELINE
600 ksps CONFIGURATION
GUIDELINE
12 x 1,000,000
Single Analog Input
1
1
REF
+ and V
= 83.33 ns
= 95.24 ns
REF
- pins following
AD
AD
by
by
both sample and hold channels. The A/D converts the
value held on one S/H channel, while the second S/H
channel acquires a new input sample.
20.7.3.2
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 600 ksps conversion rate is divided
among the different input signals. For example, four
inputs can be sampled at a rate of 150 ksps for each
signal or two inputs can be sampled at a rate of 300
ksps for each signal. Sequential sampling must be
used in this configuration to allow adequate sampling
time on each input.
20.7.3.3
The following configuration items are required to
achieve a 600 ksps conversion rate.
• Comply with conditions provided in Table 20-2
• Connect external V
• Set SSRC<2:0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Enable sequential sampling by clearing the
• Enable at least two sample and hold channels by
• Write the SMPI<3:0> control bits in the ADCON2
• Configure the A/D clock period to be:
• Configure the sampling time to be 2 T
Select at least two channels per analog input pin by
writing to the ADCHS register
the recommended circuit shown in Figure 20-2
enable the auto-convert option
control bit in the ADCON1 register
SIMSAM bit in the ADCON1 register
writing the CHPS<1:0> control bits in the
ADCON2 register
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI<3:0> = 0001 since at least two sample and
hold channels should be enabled
by writing to the ADCS<5:0> control bits in the
ADCON3 register
ing: SAMC<4:0> = 00010
12 x 600,000
Multiple Analog Input
600 ksps Configuration Items
dsPIC30F6010
1
REF
+ and V
= 138.89 ns
REF
DS70119E-page 133
- pins following
AD
by writ-