P87C52UBAA,512 NXP Semiconductors, P87C52UBAA,512 Datasheet - Page 33
![IC 80C51 MCU 8K OTP 44-PLCC](/photos/6/98/69845/568-44-plcc_sot187-2_sml.jpg)
P87C52UBAA,512
Manufacturer Part Number
P87C52UBAA,512
Description
IC 80C51 MCU 8K OTP 44-PLCC
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet
1.P87C52UBAA512.pdf
(38 pages)
Specifications of P87C52UBAA,512
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
44-PLCC
Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1250-5
935252950512
P87C52UBAA
935252950512
P87C52UBAA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P87C52UBAA,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
*
**
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
Philips Semiconductors
NOTES:
MASK ROM DEVICES
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 10) is programmed, MOVC instructions executed from
external program memory are disabled from fetching code bytes
Table 10. Program Security Bits
NOTES:
2000 Aug 07
PROGRAM LOCK BITS
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.
FOR VERIFICATION CONDITIONS SEE FIGURE 28.
SEE TABLE 8.
1
2
P0.0 – P0.7
ALE/PROG
(A0 – A12)
P1.0–P1.7
P2.0–P2.5
(D0 – D7)
PORT 0
EA/V
P2.7
P3.4
PP
**
SB1
U
P
SB2
U
U
1, 2
t
t
AVGL
DVGL
t
EHSH
PROTECTION DESCRIPTION
No Program Security features enabled.
(Code verify will still be encrypted by the Encryption Array if programmed.)
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
t
SHGL
t
GLGH
PROGRAMMING
Figure 29. EPROM Programming and Verification
ADDRESS
DATA IN
*
t
GHGL
LOGIC 0
t
t
GHDX
GHAX
33
t
GHSL
from the internal memory, EA is latched on Reset and all further
programming of the EPROM is disabled. When security bits 1 and 2
are programmed, in addition to the above, verify mode is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
LOGIC 1
t
ELQV
80C51/87C51/80C52/87C52
VERIFICATION
t
AVQV
ADDRESS
LOGIC 1
DATA OUT
*
t
EHQZ
Product specification
SU01414