P80C552IBA/08,512 NXP Semiconductors, P80C552IBA/08,512 Datasheet - Page 11
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P80C552IBA/08,512
Manufacturer Part Number
P80C552IBA/08,512
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C552EBA08512.pdf
(23 pages)
Specifications of P80C552IBA/08,512
Program Memory Type
ROMless
Package / Case
68-PLCC
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
40
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
P80C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
40
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
On-chip Adc
8-ch x 10-bit
Cpu Family
80C
Device Core
80C51
Device Core Size
8b
Frequency (max)
24MHz
Program Memory Size
Not Required
Total Internal Ram Size
256Byte
# I/os (max)
40
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1238-5
935262804512
P80C552IBA
935262804512
P80C552IBA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C552IBA/08,512
Manufacturer:
NXP
Quantity:
892
Company:
Part Number:
P80C552IBA/08,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. See Figures 10 through 15 for I
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
8. Capacitive loading on ports 0 and 2 may cause the V
9. The following condition must not be exceeded: V
10. Conditions: AV
11. The differential non-linearity (DL
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL
Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS (Continued)
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
2002 Sep 03
SYMBOL
Analog Inputs
AI
AI
AI
AV
AV
R
C
t
t
DL
IL
OS
G
A
M
C
ADS
ADC
e
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
REF
IA
e
t
e
CTC
DD
ID
PD
V
V
EA = RST = STADC = XTAL1 = V
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
current reaches its maximum value when V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
continuous conversion of AV
appropriate adjustment of gain and offset error. (See Figure 1.)
IN
REF
e
e
IH
IH
= V
= V
DD
DD
Analog supply current: operating: (16 MHz)
Analog supply current: operating: (24 MHz)
Idle mode:
Power-down mode:
Analog input voltage
Reference voltage:
Resistance between AV
Analog input capacitance
Sampling time
Conversion time (including sampling time)
Differential non-linearity
Integral non-linearity
Offset error
Gain error
Absolute voltage error
Channel to channel matching
Crosstalk between inputs of port 5
– 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V
– 0.5 V; XTAL2 not connected; Port 0 = EW = V
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
AV
AV
REF–
REF–
REF+
10, 15
= 0 V; AV
10, 14
e
IN
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
DD
10, 13
= –20 mV to 5.12 V in steps of 0.5 mV.
DD
10, 16
e
= 5.0 V, AV
) is the difference between the actual step width and the ideal step width. (See Figure 1.)
10, 11, 12
REF+
SS
test conditions.
PARAMETER
.
and AV
IN
17
REF+
is approximately 2 V.
REF–
DD
(80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
– 0.2 V < AV
OH
on ALE and PSEN to momentarily fall below the 0.9 V
DD
; EA = RST = STADC = V
2
DD
C specification, so an input voltage below 1.5 V will be recognized as a
< V
11
DD
DD
; STADC = V
+ 0.2 V.
2 V < AV
Port 5 = 0 to AV
Port 5 = 0 to AV
CONDITIONS
0–100kHz
SS
SS
TEST
max
PD
.
.
OL
OL
< AV
can exceed these conditions provided that no
s of ALE and ports 1 and 3. The noise is due
r
r
DD
DD
DD
= t
= t
f
f
= 10 ns; V
= 10 ns; V
AV
AV
MIN
SS
SS
10
80C552/83C552
DD
–0.2
–0.2
IL
IL
DD
LIMITS
= V
= V
specification when the
;
SS
SS
AV
AV
+ 0.5 V;
+ 0.5 V;
50t
MAX
8t
DD
DD
100
100
–60
1.2
1.0
50
50
50
50
50
50
50
15
0.4
CY
1
2
2
3
1
CY
+0.2
+0.2
Product data
UNIT
LSB
LSB
LSB
LSB
LSB
mA
mA
k
dB
pF
%
V
V
V
A
A
A
A
A
A
A
A
s
s