STM8S105K6U6 STMicroelectronics, STM8S105K6U6 Datasheet - Page 14

MCU 32KB FLASH EEPROM 32-VFQFPN

STM8S105K6U6

Manufacturer Part Number
STM8S105K6U6
Description
MCU 32KB FLASH EEPROM 32-VFQFPN
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet

Specifications of STM8S105K6U6

Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VFQFN, 32-VFQFPN
Processor Series
STM8S10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
25
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10123
STM8S105K6U6
Product overview
4.5
14/127
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: Four different clock sources can be used to drive the master
clock:
-
-
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
Medium density
Flash program memory
  (up to 32 Kbytes)
Data
EEPROM
memory
Figure 2: Flash memory organisation
DocID14771 Rev 10
Remains write protected during IAP
Write access possible for IAP
Data memory area ( 1 Kbyte)
Program memory area
Option bytes
UBC area
MASTER
) coming from different oscillators
(2 first pages) up to
Programmable area
from 1 Kbyte
32 Kbytes
(1 page steps)
STM8S105xx

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