ST7FLITE19F1M6 STMicroelectronics, ST7FLITE19F1M6 Datasheet - Page 129

• Manufacturer Part Number: ST7FLITE19F1M6
• Description: IC MCU 8BIT 4K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE19F1M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 12 bit / 2 x 8 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit x 10 bit
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2133-5

17 REVISION HISTORY
Table 27. Revision History
Dec-2004
July 03
Date
Revision
1.3
2.0
Revision number incremented from 1.3 to 2.0 due to Internal Document Management Sys-
tem change
Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) and added caution to PB0 and PB1
in
Changed Caution in
Removed “optional” referring to VDD in
In
tection
Replaced CRSR register by SICSR register in
Added note in
Reset delay in
MOD00 replaced by 0Ex in
Added Note 2 related to Exit from Active Halt,
Changed “Output Compare Mode” on page 57 and note 1 in
Replaced FFh by FFFh in the description of OVF bit in
Removed sentence relating to an effective change only after overflow for CK[1:0],
Replaced ICAP1 pin by LTIC Pin in
Changed
Changed
Changed “An interrupt is generated if SPIE = 1 in the SPICSR register” to “An interrupt is
generated if SPIE = 1 in the SPICR register” in description of OVR and MODF bits in
11.4.8 on page 78
Added illegal opcode detection to page 1,
Removed references to “-40°C to +125°C” temperature range in
Altered note 1 for
Changed note 2 in
Added one row in
Changed
f
In
modes
Added data for Fcpu @ 1MHz into
Updated
Added V
Changed
Added caution to
Added V
on page 110
Modified “Asynchronous RESET Pin” on page 110
Updated f
Updated ADC accuracy table values on
Changed values in ADC Characteristics table on
Added note 4 and description relating to Total Percentage in Error and Amplifier Output Off-
set Variation to the ADC Characteristics subsection and table,
Added note 5 and description relating to Offset Variation in Temperature to ADC Character-
istics subsection and table,
PLL
Changed
Added note on RC oscillator in
7.1 on page
Changed
Added note in
Changed
Added note in the description of OSC option bit and in
Table 1 on page 7
section 4.5.1 on page
section 13.4.1 on page
value of 1MHz quoted as Typical instead of a Minimum in
IL
DD
Figure 61. Typical IDD in WAIT vs. fCPU
section 11.4.2 on page 70
section 11.4.3.3 on page 73
section 13.3 on page 93
section 13.7 on page 103
SCK
section 3 on page 9
Figure 12 on page 25
section 13.3.1 on page
min value and V
row in
23: removed reference to ST7LITE10 in RCCR table
in
section 7.6.1 on page 29
section 11.1.3 on page 51
section 7.4 on page 26
section 13.10.1 on page 112
Figure 65 on page 105
section 13.2.3 on page 92
section 13.2.2 on page 92
section 13.6.3 on page 102
section 13.2.1 on page 92
section 4.4 on page 13
14: Changed 1st sentence and Clarification of Flash read-out pro-
99: Added note 5 and corrected f
IH
Figure 36 on page 57
page 117
max value in
and
section 7 on page 23
Description of Changes
(CLKIN/2, OSC/2)
93: f
Section 13.4.1 Supply Current
Figure 3
section 11.3.3.3 on page 66
CLKIN
(external clock source paragraph)
Figure 4 on page 13
page 115
changed to 30µs
section 13.8.1 on page 105
section 7.6 on page
instead of f
removing references to RESET
(PB0 and PB1)
to f
section 11.2.5 on page 59
section 7.6.3 on page 32
CPU
page 117
with correct data
(Figure 82
/4 and f
(main features) and changed
section 11.2.6 on page 60
Table 23 on page 122
OSC
CPU
CPU
section 11.2.6 on page 60
and
section 13.3.4.1 on page 95
page 117
29,
in SLOW and SLOW WAIT
/2
section 13 on page 91
table.
section 12 on page 85
Figure
and in
83)
section 13.9.1
ST7LITE1
page 60
section
129/131
section