STM32F101V8T6 STMicroelectronics, STM32F101V8T6 Datasheet - Page 27

MCU ARM 64KB FLASH/TIMER 100LQFP

STM32F101V8T6

Manufacturer Part Number
STM32F101V8T6
Description
MCU ARM 64KB FLASH/TIMER 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F101V8T6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
10 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
100
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-6060

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F101V8T6
Manufacturer:
DEUTSCH
Quantity:
5 000
STM32F101x8, STM32F101xB
Table 4.
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
39
40
41
42
43
44
45
46
47
48
-
-
-
-
-
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
55
56
57
58
59
60
61
62
63
64
Pins
-
-
-
-
-
100
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Medium-density STM32F101xx pin definitions (continued)
30
31
32
33
34
35
36
1
-
-
-
-
-
-
-
Pin name
BOOT0
V
V
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
SS_3
DD_3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
S
I
Doc ID 13586 Rev 14
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
(after reset)
function
JNTRST
BOOT0
V
JTDO
V
Main
PD5
PD6
PD7
PB5
PB8
PB9
PE0
PE1
PB6
PB7
DD_3
SS_3
(3)
Table 2 on page
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
I2C1_SDA
I2C1_SCL
I2C1_SMBAl
TIM4_ETR
Default
Alternate functions
Pinouts and pin description
11.
(8)
(8)
(8)
(8)
(8)
(8)
/
/
TIM2_CH2 / PB3
PB4 / TIM3_CH1
USART2_RX
USART2_CK
USART1_RX
USART2_TX
TRACESWO
USART1_TX
TIM3_CH2 /
SPI1_MISO
SPI1_MOSI
(3)(4)
SPI1_SCK
I2C1_SDA
I2C1_SCL
Remap
27/87

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