EZ80F91NA050EG Zilog, EZ80F91NA050EG Datasheet - Page 184
EZ80F91NA050EG
Manufacturer Part Number
EZ80F91NA050EG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3869
EZ80F91NA050EG
EZ80F91NA050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Universal Asynchronous
Receiver/Transmitter
PS019215-0910
The UART module implements all of the logic required to support the asynchronous com-
munications protocol. The module also implements two separate 16-byte-deep FIFOs for
both transmission and reception. A block diagram of the UART is displayed in
The UART module provides the following asynchronous communications protocol-
related features and functions:
•
•
•
•
•
•
5-, 6-, 7-, 8- or 9-bit data transmission.
Even/odd, space/mark, address/data, or no parity bit generation and detection.
Start and stop bit generation and detection (supports up to two stop bits).
Line break detection and generation.
Receiver overrun and framing errors detection.
Logic and associated I/O to provide modem handshake capability.
Interrupt Signal
System Clock
I/O Address
Data
Figure 36. UART Block Diagram
Universal Asynchronous Receiver/Transmitter
Transmit
Receive
Modem
Control
Buffer
Buffer
Logic
Product Specification
eZ80F91 MCU
RxD0/RxD1
TxD0/TxD1
CTS0/CTS1
RTS0/RTS1
DSR0/DSR1
DTR0/DTR1
DCD0/DCD1
RI0/RI1
Figure
36.
175
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