EZ80F91NA050EG Zilog, EZ80F91NA050EG Datasheet - Page 334
EZ80F91NA050EG
Manufacturer Part Number
EZ80F91NA050EG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3869
EZ80F91NA050EG
EZ80F91NA050EG
Available stocks
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Manufacturer
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Price
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Table 216. EMAC Interrupt Status Register
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
TxFSMERR_STAT
6
MGTDONE_STAT
5
Rx_CF_STAT
4
Rx_PCF_STAT
3
Rx_DONE_STAT
2
Rx_OVR_STAT
Note:
EMAC Interrupt Status Register
When a Receive overrun occurs, all incoming packets are ignored until the
Rx_OVR_STAT status bit is cleared by software. Consequently, software controls when
the receiver is re-enabled after an overrun. Enable the Rx_OVR interrupt to detect overrun
conditions when they occur. Clear this condition when the Rx buffers are freed to avoid
additional overrun errors. See
Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the selected
bit.
Value
1
0
1
0
1
0
1
0
1
0
1
0
R/W
7
0
Description
An internal error occurs in the EMAC Transmit path. The
Transmit path must be reset to reset this error condition.
Normal operation—no Transmit state machine errors.
The MII Management interrupt has completed a Read
(RSTAT or SCAN) or a Write (LDCTLD) access to the
PHY.
The MII Management interrupt does not occur.
Receive Control Frame interrupt (Receive Interrupt)
occurs.
Receive Control Frame interrupt does not occur.
Receive Pause Control Frame interrupt (Receive
Interrupt) occurs.
Disable Receive Pause Control Frame interrupt (Receive
Interrupt) does not occur.
Receive Done interrupt (Receive Interrupt) occurs.
Disable Receive Done interrupt (Receive Interrupt) does
not occur.
Receive Overrun interrupt (System Interrupt) occurs.
Receive Overrun interrupt (System Interrupt) does not
occur.
R/W
6
0
R/W
5
0
Table
(EMAC_ISTAT = 004Dh)
R/W
4
0
216.
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
325
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