EZ80F91NA050EG Zilog, EZ80F91NA050EG Datasheet - Page 258
EZ80F91NA050EG
Manufacturer Part Number
EZ80F91NA050EG
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3869
EZ80F91NA050EG
EZ80F91NA050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 140. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register Write Only
Address Space)
PS019215-0910
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register must only be written during ZDI DEBUG mode (that is,
following a break). See
Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register Write Only address
space. They are written with instruction data for direct execution by the CPU. When the
ZDI_IS0 register is written, the eZ80F91 device exits the ZDI break state and executes a
single instruction. The opcodes and operands for the instruction come from these Instruc-
tion Store registers. The Instruction Store Register 0 is the first byte fetched, followed by
Instruction Store registers 1, 2, 3, and 4, as necessary. Only the bytes the CPU requires to
execute the instruction must be stored in these registers. Some CPU instructions, when
combined with the MEMORY mode suffixes (.SIS, .SIL, .LIS, or .LIL), require 6 bytes to
Value
0
1
0
1
000000
W
7
0
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK, is
not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass control
of the address and data buses to an external peripheral.
Reserved.
W
6
0
Table
W
5
0
140.
W
4
0
W
3
0
W
2
0
W
1
0
Product Specification
W
0
0
Zilog Debug Interface
eZ80F91 MCU
249
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