M37544G2AGP#U0 Renesas Electronics America, M37544G2AGP#U0 Datasheet - Page 30

• Manufacturer Part Number: M37544G2AGP#U0
• Description: IC 740 MCU OTP 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37544G2AGP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: QzROM
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.1.04
REJ03B0012-0104Z
7544 Group
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Fig. 30 Block diagram of UART serial I/O
Fig. 31 Operation of UART serial I/O function
Transmit or receive clock
Transmit buffer write
Receive buffer read
Serial output T
Serial input R
Notes
2004.06.08
P1
P1
P1
2
0
1
/S
/R
/T
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
CLK
X
X
X
signal
signal
D
IN
D
interrupt source selection bit (TIC) of the serial I/O control register.
X
X
D
D
ST detector
BRG count source selection bit
TBE=0
page 28 of 66
1/4
TSC=0
TBE=1
Character length selection bit
Character length selection bit
ST
ST
8 bits
7 bits
Serial I/O synchronous clock selection bit
OE
D
D
0
0
Address 0018
TBE=0
D
D
1
1
PE FE
Receive shift register
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer register
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Data bus
Data bus
16
Baud rate generator
Transmit buffer register
Transmit shift register
SP detector
Address 001C
Address
Serial I/O control register
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
1/16
16
RBF=1
SP
SP
Clock control circuit
0018
TBE=1
16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST
ST
Transmit interrupt source selection bit
Serial I/O status register
D
0
D
0
RBF=0
Address 001A
D
1/16
D
1
1
Transmit buffer empty flag (TBE)
Transmit shift completion flag (TSC)
UART control register
Generated at 2nd bit in 2-stop-bit mode
Transmit interrupt request (TI)
16
Address
Address 001B
0019
16
16
TSC=1
SP
RBF=1
SP