R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 506
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
0.20
REVISION HISTORY
Jan 16, 2006
Date
30 to 67
56 to 66
Page
27
28
33
34
46
47
49
50
51
67
69
71
72
73
75
77
78
79
80
81
82
5.2 Power-On Reset Function “When a capacitor is ... or more.” added
Figure 5.7 Example of Power-On Reset Circuit and Operation revised
5.4 Voltage Monitor 1 Reset;
“6. Programmable I/O Ports” → “6. Voltage Detection Circuit” and
“7. Voltage Detection Circuit” → “7. Programmable I/O Ports” revised
Figure 6.5 Registers VCA1 and VCA2; VCA2 register revised
Figure 6.6 VW0C Register revised
Figure 7.2 Configuration of Programmable I/O Ports (2) revised
Figure 7.3 Configuration of Programmable I/O Ports (3) revised
Figure 7.5 Configuration of Programmable I/O Ports (5) revised
Figure 7.6 Configuration of Programmable I/O Ports (6) revised
Figure 7.7 Configuration of Programmable I/O Ports (7) revised
7.4 Port setting added;
Table 7.48 Unassigned Pin Handling revised
9. Bus revised;
Table 9.2 Bus Cycles by Access Space of the R8C/25 Group added,
Table 9.3 Access Unit and Bus Operations;
Figure 10.1 Clock Generation Circuit revised
Figure 10.2 CM0 Register revised
Figure 10.3 CM1 Register revised
Figure 10.5 Registers FRA0 and FRA1; FRA0 register revised
Figure 10.8 VCA2 Register added
Figure 10.9 Examples of XIN Clock Connection Circuit revised
10.2.2 High-Speed On-Chip Oscillator Clock;
10.3 XCIN Clock “To input an external clock ... pin open.” added
10.4.2 CPU Clock “Use the XCIN clock while ... stabilizes.” added
10.4.3 Peripheral Function Clock (f1, f2, f4, f8, f32, fC4, and fC32);
10.4.5 fOCO40M;
10.4.8 fOCO128 added
Table 10.2 Settings and Modes of Clock Associated Bits revised
R8C/24 Group, R8C/25 Group Hardware Manual
“When ... VCC pin drops the Vdet1 ...” → “When ... VCC pin reaches to
the Vdet1 ...” revised
Table 7.4 Port P0_0/AN7 to Table 7.47 Port P6_7/INT3/RXD1 added
“However, only following SFRs are ... accessed at a time.” added
“SFR” → “SFR, data flash”,
“ROM/RAM” → “ROM (program ROM), RAM” revised
“To use the high-speed on-chip ... or more).” added
“Use fC4 and fC32 while the XCIN clock oscillation stabilizes.” added
“fOCO40M can be ... supply voltage VCC = 3.0 to 5.5 V.” added
C - 2
Description
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