MC908GR60ACFAE Freescale Semiconductor, MC908GR60ACFAE Datasheet
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MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A Data Sheet M68HC08 Microcontrollers MC68HC908GR60A Rev. 5 04/2007 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006, 2007. All rights reserved. ...
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... Electrical — Updated tables Page Number(s) N/A 119 174 179 180 122 28 131 174 233 251 264 269 279 284 122 154 156 — 179 180 222 223 279 281 — Updated section to 284 284 285 Freescale Semiconductor ...
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... Chapter 17 Timer Interface Module (TIM1 .225 Chapter 18 Timer Interface Module (TIM2 .241 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 295 Appendix A MC68HC908GR48A 305 Appendix B MC68HC908GR32A 309 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 5 ...
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... List of Chapters MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Freescale Semiconductor ...
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... FLASH-1 Control and Block Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.2.1 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.2.2 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6.3 FLASH-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.4 FLASH-1 Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.5 FLASH-1 Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 1 General Description and and DDA SSA /V ...
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... Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8.2.3 Left Justified Signed Data Mode 3.8.2.4 Eight Bit Truncation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SSAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 REFL ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Freescale Semiconductor ...
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... Acquisition/Lock Time Specifications 4.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.8.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 4 Clock Generator Module (CGM DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SSA Chapter 5 Configuration Register (CONFIG) 9 ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.4 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.6 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 6 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Freescale Semiconductor ...
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... Keyboard Interrupt Module (KBI 123 10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.9 Low-Voltage Inhibit Module (LVI 123 10.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes 11 ...
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... Data Direction Register 138 12.5 Port 140 12.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.5.2 Data Direction Register 140 12.5.3 Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output (I/O) Ports Freescale Semiconductor ...
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... ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.7.1 PTE0/TxD (Transmit Data 165 13.7.2 PTE1/RxD (Receive Data 165 13.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.8.1 ESCI Control Register 166 13.8.2 ESCI Control Register 167 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 13 13 ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 14 System Integration Module (SIM) Freescale Semiconductor ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.5 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.7 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 15 Chapter 16 Timebase Module (TBM) 15 ...
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... Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.6 TIM2 During Break Interrupts 251 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 17 Timer Interface Module (TIM1) Chapter 18 Timer Interface Module (TIM2) Freescale Semiconductor ...
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... Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 20.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 20.5 5.0-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 20.6 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 20.7 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 20.8 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 19 Development Support Chapter 20 Electrical Specifications 17 ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 A.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 A.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 B.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 B.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 B.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 21 Appendix A MC68HC908GR48A Appendix B MC68HC908GR32A Freescale Semiconductor ...
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... Standard low-power modes of operation: – Wait mode – Stop mode 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor and Appendix B MC68HC908GR32A. (1) 19 ...
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... Port C is only 2 bits: PTC0–PTC1 – Port D is only 7 bits: PTD0–PTD6; shared with SPI, TIM1 and TIM2 modules – Port E is only 2 bits: PTE0–PTE1; shared with ESCI module MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Freescale Semiconductor ...
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... Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GR60A. Refer to Appendix B MC68HC908GR32A. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor MCU Block Diagram Appendix A MC68HC908GR48A and 21 ...
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... MODULE PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7–PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1 (2, 3) PTC0 (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...
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... Figure 1-4 and 64-pin QFP respectively. RST PTE0/TxD PTE1/RxD IRQ PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor illustrate the pin assignments for the 32-pin LQFP, 48-pin LQFP Pin Assignments 24 ...
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... PTE0/TxD 2 PTE1/RxD 3 PTE2 4 PTE3 5 PTE4 6 PTE5 7 IRQ 8 PTD0/SS/MCLK 9 PTD1/MISO 10 PTD2/MOSI 11 PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev PTA2/KBD2/AD10 36 PTA1/KBD1/AD9 35 PTA0/KBD0/AD8 34 PTC6 33 PTC5 SSAD REFL DDAD REFH PTB7/AD7 29 PTB6/AD6 28 PTB5/AD5 27 PTB4/AD4 26 PTB3/AD3 25 Freescale Semiconductor ...
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... Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
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... Figure 1-5. Power Supply Bypassing and V ) DDA SSA /V DDAD REFH is the high reference supply for the ADC, and by default REFH V SS Chapter 4 Chapter Chapter 4 Clock Generator Module Chapter 4 Clock Generator Module and SSAD REFL and V REFH Freescale Semiconductor REFL . DD ...
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... Port F I/O Pins (PTF7/T2CH5–PTF0) PTF7–PTF4 are special-function, bidirectional I/O port pins that can be individually programmed to be timer interface module (TIM2) pins. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor . See Chapter 3 Analog-to-Digital Converter SS Chapter 12 Input/Output (I/O) ...
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... Since some general-purpose I/O pins are not available on all packages, these pins must be terminated as well. Either method above are appropriate. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 17 Timer Interface Module and Chapter 12 Input/Output (I/O) (ADC Ports. Chapter 12 Freescale Semiconductor ...
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... FLASH-1 block protect register, FL1BPR • $FF81; FLASH-2 block protect register, FL2BPR • $FF88; FLASH-1 control register, FL1CR Data registers are shown in Figure MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 2-2. Table 2 list of vector locations. Figure 2-1, includes: 29 ...
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... FLASH-1 BLOCK PROTECT REGISTER (FL1BPR) $FF81 FLASH-2 BLOCK PROTECT REGISTER (FL2BPR) $FF82 RESERVED ↓ 6 BYTES $FF87 $FF88 FLASH-1 CONTROL REGISTER (FL1CR) $FF89 RESERVED ↓ 67 BYTES $FFCB $FFCC FLASH-1 VECTORS ↓ 52 BYTES (1) $FFFF 1. $FFF6–$FFFD used for eight security bytes Freescale Semiconductor ...
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... See page 179. Reset: Read: ESCI Arbiter Data $000B Register (SCIADAT) Write: See page 180. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 ...
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... SCTIE TCIE SCRIE ILIE SCTE TC SCRF IDLE Unimplemented R = Reserved Bit 0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF Unaffected Freescale Semiconductor ...
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... Register Low (T1CNTL) Write: See page 235. Reset: Read: TIM1 Counter Modulo $0023 Register High (T1MODH) Write: See page 236. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit Unaffected by reset ...
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... Indeterminate after reset Bit Indeterminate after reset TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit Unimplemented R = Reserved Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit Unaffected Freescale Semiconductor ...
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... Read: PLL VCO Select Range $003A Register (PMRS) Write: See page 84. Reset: Read: $003B Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit CH0F CH0IE MS0B MS0A Bit 15 ...
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... Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 A3 AD2 AD1 AD0 0 MODE1 MODE0 PTAF3 PTF2 PTF1 PTF0 PTG3 PTG2 PTG1 PTG0 DDRF3 DDRF2 DDRF1 DDRF0 DDRG3 DDRG2 DDRG1 DDRG0 KBIP3 KBIP2 KBIP1 KBIP0 ELS2B ELS2A TOV2 CH2MAX Bit Bit Unaffected Freescale Semiconductor ...
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... Writing a 0 clears SBSW. Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 199. POR: Read: $FE02 Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit CH3F 0 CH3IE MS3A Bit 15 ...
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... IF6 IF5 IF4 IF3 IF14 IF13 IF12 IF11 IF22 IF21 IF20 IF19 Bit Bit BRKE BRKA LVIOUT Unimplemented R = Reserved Bit IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 IF24 IF23 HVEN MASS ERASE PGM Bit Bit Unaffected Freescale Semiconductor ...
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... See page 42. Reset: Read: COP Control Register $FFFF (COPCTL) Write: See page 95. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Vector Priority Lowest MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit BPR7 BPR6 BPR5 BPR7 BPR6 BPR5 ...
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... TIM1 Channel 0 Vector (Low) $FFF8 PLL Vector (High) IF2 $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) Vector Freescale Semiconductor ...
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... FLASH-1 control register (FL1CR) • $FFCC–$FFFF: these locations are reserved for user-defined interrupt and reset vectors (see Table 2-1 for details) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Random-Access Memory (RAM) NOTE NOTE NOTE 41 ...
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... Memory Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents. 2.6.2 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its operation, the FLASH-1 control register (FL1CR) and the FLASH-1 block protect register (FL1BPR) ...
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... With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-1 array. START ADDRESS OF FLASH BLOCK PROTECT Figure 2-5. FLASH-1 Block Protect Start Address FL1BPR[7:0] MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor BPR6 BPR5 ...
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... Therefore, if this page is not protected by FL1BPR and the vector locations are erased by either a page or a mass erase operation, then both FL1BPR and FL2BPR will also get erased. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Figure 2-1 and make sure that the NOTE NOTE Freescale Semiconductor ...
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... However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE (minimum 4 ms). NOTE FLASH-1 Memory (FLASH-1) ...
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... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev NOTE Freescale Semiconductor ...
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... PROG programming time to the same row before next erase PROG X NVS NVH PGS MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 2-6. NOTE maximum defined as the cumulative high voltage HV HV must satisfy this condition: HV ≤ ...
Page 48
... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a standby mode. Standby mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev NOTE Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-6. FLASH-1 Programming Algorithm Flowchart MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 1 SET PGM BIT READ THE FLASH BLOCK 2 PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ...
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... FL2BPR physically resides within FLASH-1 memory addressing space • $FE08: FLASH-2 control register (FL2CR) Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents. 2.7.2 FLASH-2 Control and Block Protect Registers The FLASH-2 array has two registers that control its operation, the FLASH-2 control register (FL2CR) and the FLASH-2 block protect register (FL2BPR) ...
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... FLASH-2 is protected from this start address to the end of FLASH-2 memory at $7FFF. With this mechanism, the protect start address can be $XX00 and $XX80 (128 byte page boundaries) within the FLASH-2 array. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
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... NOTE ↓ ↓ Figure 2-1 and make sure that the Freescale Semiconductor ...
Page 53
... FLASH array memory space such as the COP control register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/erase operations. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Register. If FL2BPR is programmed with any value other than $FF, the NOTE NOTE (minimum 4 ms) ...
Page 54
... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev NOTE Freescale Semiconductor ...
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... PROG programming time to the same row before next erase PROG X NVS NVH PGS MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 2-10. NOTE maximum defined as the cumulative high voltage HV HV must satisfy this condition: HV ≤ ...
Page 56
... FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a standby mode. Standby mode is the power saving mode of the FLASH module, in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is minimum. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev NOTE Freescale Semiconductor ...
Page 57
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-10. FLASH-2 Programming Algorithm Flowchart MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 1 SET PGM BIT READ THE FLASH BLOCK 2 PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ...
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... Memory MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Freescale Semiconductor ...
Page 59
... I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. A read of a port pin in use by the ADC will return a 0. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ). V is converted by ADIN ...
Page 60
... MODULE PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7–PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1 (2, 3) PTC0 (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...
Page 61
... V . DDAD Connect the V DDAD connect the V SSAD The V pin should be routed carefully for maximum noise immunity. DDAD MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor DDRx PTx DISABLE ADC DATA REGISTER ADC VOLTAGE IN (V ADIN ADC ADC CLOCK CLOCK GENERATOR ADIV2– ...
Page 62
... MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev ADC cycles Conversion time = ADC frequency Freescale Semiconductor ...
Page 63
... The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 3-3 ...
Page 64
... External filtering is often necessary to ensure a clean V DD NOTE carefully and place bypass REFH may improve common mode noise rejection. pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD REFH REFH close and REFH Freescale Semiconductor for ...
Page 65
... Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) The write function of the COCO bit is reserved. When writing to the ADSCR register, always have the COCO bit position. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ) REFL as its lower voltage reference pin. By default, connect the V REFL ...
Page 66
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 Table 3-1. Care should be taken (1) Input Select PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 PTA0/KBD0/AD8 PTA1/KBD1/AD9 PTA2/KBD2/AD10 PTA3/KBD3/AD11 PTA4/KBD4/AD12 PTA5/KBD5/AD13 PTA6/KBD6/AD14 PTA7/KBD7/AD15 Continued on next page Freescale Semiconductor ...
Page 67
... ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed. Address: $003D Bit 7 Read: AD9 Write: Reset: Address: $003E Read: AD1 Write: Reset: Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor (1) ADCH2 ADCH1 ADCH0 ...
Page 68
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Unaffected by reset AD6 AD5 AD4 AD3 Unaffected by reset = Unimplemented AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented ADRH 2 1 Bit 0 0 AD9 AD8 ADRL AD2 AD1 AD0 2 1 Bit 0 AD4 AD3 AD2 Freescale Semiconductor ...
Page 69
... ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. ADIV2 Don’t care MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Unaffected by reset AD8 AD7 AD6 ...
Page 70
... ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev bus frequency CGMXCLK ≅ 1 MHz = ADIV[2:0] 20.10 5.0-Volt ADC Characteristics. Freescale Semiconductor ...
Page 71
... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 71 ...
Page 72
... LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF Figure 4-1. CGM Block Diagram CGMXCLK (TO: SIM, TBM, ADC) A CGMOUT CLOCK SELECT ÷ 2 (TO SIM CIRCUIT SIMDIV2 * WHEN CGMOUT = B (FROM SIM) CGMVCLK CGMINT (TO SIM) Freescale Semiconductor ...
Page 73
... The circuit determines the mode of the PLL and the lock condition based on this RCLK comparison. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor VRS , (71.4 kHz) times a linear factor, L, and a power-of-two factor PLL.) Modes. The value of the external capacitor and the Functional Description ...
Page 74
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 4.8 Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications Register.) Register.) 4.5.2 PLL 4.3.8 Base Clock Selector for for Freescale Semiconductor ...
Page 75
... The relationship between the VCO frequency, f reference frequency, f RCLK N, the range multiplier, must be an integer. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor , after entering tracking mode before selecting the PLL as the AL Table 4-1. Variable Definitions Definition ...
Page 76
... VCLK L = Round NOM VRS NOM E × NOM ≤ -------------------------- - – VRS VCLK VCLK VRS VCLKDES NOTE to a value determined RCLK Chapter 20 Electrical and f . VCLK BUS Table 4- (1) 2 VRS and f . For proper operation, VCLKDES , and f must be as close as possible VRS Freescale Semiconductor . The ...
Page 77
... L is programmed This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 4-3. Numeric Example f RCLK ...
Page 78
... Note: Filter network in box can be replaced with a single capacitor, but will degrade stability. 4.4 I/O Signals The following paragraphs describe the CGM I/O signals. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev CGMXCLK CGMXFC OSC2 Figure 4-2. CGM External Connections Figure V V SSA DDA V DD CBYP C F2 Freescale Semiconductor 4-2. ...
Page 79
... OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start up. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 4-2.) NOTE ) ...
Page 80
... PLLF PLLIE PLLON LOCK AUTO ACQ MUL7 MUL6 MUL5 VRS7 VRS6 VRS5 Unimplemented Figure 4-3. CGM I/O Register Summary BCS R R VPR1 MUL11 MUL10 MUL9 MUL4 MUL3 MUL2 MUL1 VRS4 VRS3 VRS2 VRS1 Reserved Freescale Semiconductor Bit 0 VPR0 MUL8 0 MUL0 0 VRS0 ...
Page 81
... CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 82
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Circuit.). VRS 4.3.3 PLL Circuits, Register.) VCO Power-of-Two ( NOTE 4.3.6 Programming the PLL LOCK 0 0 ACQ Reserved . VPR1:VPR0 cannot be written when the 4.3.6 Programming the Range Multiplier for detailed instructions 2 1 Bit Freescale Semiconductor PLL, and ...
Page 83
... Reset initializes the registers to $0040 for a default multiply value of 64. The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as 0s. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 84
... PLL Circuits and 4.3.6 Programming the NOTE VRS6 VRS5 VRS4 VRS3 NOTE for detailed instructions on selecting the proper value 2 1 Bit 0 MUL2 MUL1 MUL0 PLL.) MUL7–MUL0 cannot 2 1 Bit 0 VRS2 VRS1 VRS0 4.3.6 Freescale Semiconductor ...
Page 85
... WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor PLL, and 4.5.1 PLL Control . VRS7– ...
Page 86
... Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev 14.7.3 Break Flag Control Register.) Freescale Semiconductor ...
Page 87
... CGMXFC SSA (A) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Acquisition/Lock Time Specifications PLL.) 4.8.3 Choosing a . The power supply potential alters the DDA Time, the external filter network is critical to the Figure 4-9 Figure 4-9 (A) ...
Page 88
... Table 4-5. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev 8.2 nF 820 pF 4.7 nF 470 pF 3.3 nF 330 pF 2.2 nF 220 pF 1.8 nF 180 pF 1.5 nF 150 pF 1.2 nF 120 100 2.2 nF Freescale Semiconductor ...
Page 89
... POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 5-1 and Figure 5-2 ...
Page 90
... Clock divided Clock divided by 4 Chapter 16 Timebase Module (TBM) (CGM). This function is used to keep the timebase running while Chapter 16 Timebase Module Module Bit 0 TMBCLKSEL OSCENINSTOP SCIBDSRC Clock for a more (TBM). When clear, the oscillator will Chapter 13 Enhanced Serial Freescale Semiconductor ...
Page 91
... SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles Exiting stop mode by any reset will result in the long stop recovery. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor LVISTOP ...
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... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev Chapter 6 Computer Operating Properly (COP) Module. Freescale Semiconductor ...
Page 93
... COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 6-1. COP Block Diagram ...
Page 94
... The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the SIM counter and the COP counter. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev NOTE . During the break state, TST NOTE Figure 6-1. 6.4 Freescale Semiconductor ...
Page 95
... Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 96
... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev present on the RST pin. TST Freescale Semiconductor ...
Page 97
... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 97 ...
Page 98
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...
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... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
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... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 100 NOTE 2 1 Bit Freescale Semiconductor ...
Page 101
... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 101 ...
Page 102
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 103
... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...
Page 104
... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...
Page 105
... ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...
Page 106
... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...
Page 107
... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...
Page 108
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 109
... When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set until both of these events occur: • Vector fetch or software clear • Return of the interrupt pin to a high level MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 109 ...
Page 110
... CLR D Q SYNCHRONIZER CK IMASK MODE Figure 8-1. IRQ Module Block Diagram NOTE Bit Unimplemented Figure 8-2. IRQ I/O Register Summary TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ INTERRUPT REQUEST HIGH TO MODE SELECT VOLTAGE DETECT LOGIC IRQF 0 IMASK ACK Freescale Semiconductor Bit 0 MODE 0 ...
Page 111
... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Support. IRQ Pin ...
Page 112
... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 112 IRQF Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 113
... A keyboard interrupt is latched when one or more keyboard pins are asserted. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 113 ...
Page 114
... MODULE PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7–PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1 (2, 3) PTC0 (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...
Page 115
... See page 118. Reset: Read: Keyboard Interrupt Enable $001B Register (INTKBIER) Write: See page 119. Reset: Read: Keyboard Interrupt Polarity $0448 Register (INTKBIPR) Write: See page 119. Reset: MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor V DD CLR MODEK Bit ...
Page 116
... KBIPx bits in the keyboard interrupt polarity register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 116 NOTE Freescale Semiconductor ...
Page 117
... These registers control and monitor operation of the keyboard module: • Keyboard status and control register (INTKBSCR) • Keyboard interrupt enable register (INTKBIER) • Keyboard interrupt polarity register (INTKBIPR) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 9.7.1 Keyboard Status and Control Low-Power Modes Register. 117 ...
Page 118
... This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on edge and level detect 0 = Keyboard interrupt requests on edges only MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 118 KEYF Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...
Page 119
... Each of these read/write bits enables the polarity of the keyboard interrupt pin. Reset clears the keyboard interrupt polarity register Keyboard polarity is rising edge and/or high level 0 = Keyboard polarity is falling edge and/or low level MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 120
... Keyboard Interrupt Module (KBI) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 120 Freescale Semiconductor ...
Page 121
... SBSW bit in the break status register is set. 10.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Chapter 5 Configuration Register 121 ...
Page 122
... The STOP bit in the CONFIG1 register enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 122 Freescale Semiconductor ...
Page 123
... MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor External Interrupt Module (IRQ) 123 ...
Page 124
... In stop mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 124 Freescale Semiconductor ...
Page 125
... Timebase module (TBM) interrupt — A CPU interrupt request from the TBM loads the program counter with the contents of: $FFDC and $FFDD; TBM interrupt. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Exiting Wait Mode voltage resets TRIPF 125 ...
Page 126
... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal unless the OSCENINSTOP bit is set. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 126 TRIPF NOTE voltage resets the MCU Freescale Semiconductor ...
Page 127
... V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...
Page 128
... V DD TRIPF to remain above the V level, enabling LVI resets allows the LVI TRIPF falls below the V level. In the configuration register, the DD TRIPF , which causes the MCU TRIPR LVISTOP FROM CONFIG1 LVI RESET level, software can monitor V DD Freescale Semiconductor Bit polling ...
Page 129
... Reset clears the LVIOUT bit. V 11.5 LVI Interrupts The LVI module does not generate interrupt requests. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until DD TRIPF . This prevents a condition in which the MCU is ...
Page 130
... If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 130 Freescale Semiconductor ...
Page 131
... Write: See page 138. Reset: Read: Port C Data Register $0002 (PTC) Write: See page 140. Reset: Figure 12-1. I/O Port Register Summary (Sheet MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset ...
Page 132
... PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Unimplemented Bit 0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Freescale Semiconductor ...
Page 133
... DDRA6 7 DDRA7 0 DDRB0 1 DDRB1 2 DDRB2 3 DDRB3 B ADC 4 DDRB4 5 DDRB5 6 DDRB6 7 DDRB7 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit PTF7 PTF6 PTF5 PTF4 Unaffected by reset PTG7 PTG6 PTG5 PTG4 Unaffected by reset DDRF7 DDRF6 DDRF5 DDRF4 DDRG7 DDRG6 DDRG5 ...
Page 134
... PTC3 PTC4 PTC5 PTC6 PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK — PTD4/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTE0/TxD PTE1/RxD PTE2 — PTE3 PTE4 PTE5 PTF0 PTF1 PTF2 PTF3 — PTF4/T2CH2 PTF5/T2CH3 PTF6/T2CH4 PTF7/T2CH5 PTG0/AD16 PTG1/AD17 PTG2/AD18 PTG3/AD19 — PTG4/AD20 PTG5/AD21 PTG6/AD22 PTG7/AD23 Freescale Semiconductor ...
Page 135
... PTAx/KBDx/ADx pin, while PTA is read as a digital input during the CPU read cycle. Those ports not selected as analog input channels are considered digital I/O ports. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor PTA6 ...
Page 136
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 136 DDRA6 DDRA5 DDRA4 DDRA3 NOTE Table 12-2 summarizes the operation of the port A pins. DDRAx RESET PTAx Figure 12-4. Port A I/O Circuit 2 1 Bit 0 DDRA2 DDRA1 DDRA0 PTAPUEx INTERNAL PULLUP DEVICE PTAx Freescale Semiconductor ...
Page 137
... These writable bits are software programmable to enable pullup devices on an input port bit Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-2. Port A Pin Functions Accesses to DDRA I/O Pin ...
Page 138
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 138 PTB6 PTB5 PTB4 Unaffected by reset AD6 AD5 AD4 Figure 12-6. Port B Data Register (PTB) NOTE DDRB6 DDRB5 DDRB4 DDRB3 Bit 0 PTB3 PTB2 PTB1 PTB0 AD3 AD2 AD1 AD0 2 1 Bit 0 DDRB2 DDRB1 DDRB0 Freescale Semiconductor ...
Page 139
... X Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Table 12-3 summarizes the operation of the port B pins. DDRBx RESET PTBx Figure 12-8. Port B I/O Circuit Table 12-3 ...
Page 140
... C bits from MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 140 NOTE PTC6 PTC5 PTC4 PTC3 Unaffected by reset Figure 12-9. Port C Data Register (PTC DDRC6 DDRC5 DDRC4 DDRC3 NOTE 2 1 Bit 0 PTC2 PTC1 PTC0 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...
Page 141
... I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-4 summarizes the operation of the port C pins. DDRCx RESET PTCx Figure 12-11. Port C I/O Circuit Table 12-4 ...
Page 142
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 142 PTCPUE5 PTCPUE4 PTCPUE3 PTD6 PTD5 PTD4 PTD3 Unaffected by reset T2CH0 T1CH1 T1CH0 SPSCK Chapter 17 Timer Interface Module (TIM1 Bit 0 PTCPUE2 PTCPUE1 PTCPUE0 Bit 0 PTD2 PTD1 PTD0 MOSI MISO SS MCLK and Chapter 18 Freescale Semiconductor ...
Page 143
... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 12-15 shows the port D I/O logic. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 17 Timer Interface Module (TIM1) (TIM2). Table 12-5. ...
Page 144
... Table 12-5. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write (2) Input, V DDRD7–DDRD0 DD (4) DDRD7–DDRD0 Input, Hi-Z Output DDRD7–DDRD0 V DD PTDPUEx INTERNAL PULLUP DEVICE PTDx Accesses to PTD Read Write Pin PTD7–PTD0 Pin PTD7–PTD0 PTD7–PTD0 PTD7–PTD0 Freescale Semiconductor (3) (3) ...
Page 145
... Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the ESCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 146
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 146 Chapter 13 Enhanced Serial Communications Interface (ESCI DDRE5 DDRE4 DDRE3 NOTE Table 12-6 summarizes the operation of the port E pins. Module Bit 0 DDRE2 DDRE1 DDRE0 Freescale Semiconductor ...
Page 147
... PTF7–PTF0 — Port F Data Bits These read/write bits are software-programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on port F data. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor DDREx RESET PTEx Figure 12-19 ...
Page 148
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 148 Chapter 17 Timer Interface Module (TIM1 DDRF6 DDRF5 DDRF4 DDRF3 NOTE DDRFx RESET PTFx Figure 12-22. Port F I/O Circuit Table 12-7 summarizes the operation of the port F pins. and Chapter Bit 0 DDRF2 DDRF1 DDRF0 PTFx Freescale Semiconductor ...
Page 149
... PTG is read as a digital input during the CPU read cycle. Those ports not selected as analog input channels are considered digital I/O ports. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-7. Port F Pin Functions Accesses to DDRF Read/Write (2) DDRF7– ...
Page 150
... Figure 12-25. Port G I/O Circuit Table 12-8 summarizes the operation of the port G pins. Table 12-8. Port G Pin Functions Accesses to DDRG Read/Write (2) DDRG7–DDRG0 DDRG7–DDRG0 2 1 Bit 0 DDRG2 DDRG1 DDRG0 PTGx Accesses to PTG Read Write Pin PTG7–PTG0 PTG7–PTG0 PTG7–PTG0 Freescale Semiconductor (3) ...
Page 151
... Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 151 ...
Page 152
... MODULE PTA7/KBD7/AD15– (2) PTA0/KBD0/AD8 PTB7/AD7–PTB0/AD0 (2) PTC6 (2) PTC5 (2, 3) PTC4 (2, 3) PTC3 (2, 3) PTC2 (2, 3) PTC1 (2, 3) PTC0 (2) PTD7/T2CH1 (2) PTD6/T2CH0 (2) PTD5/T1CH1 (2) PTD4/T1CH0 (2) PTD3/SPSCK (2) PTD2/MOSI (2) PTD1/MISO (2) PTD0/SS/MCLK PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 (3) PTF3–PFT0 PTG7/AD23– PTG0/AD16 Freescale Semiconductor ...
Page 153
... BIT BIT 0 BIT 1 START BIT BIT 0 BIT 1 MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-1 shows the full names and the generic names of the Table 13-1. Pin Name Conventions RxD PTE1/RxD 8-BIT DATA FORMAT OR DATA (BIT M IN SCC1 CLEAR) ...
Page 154
... ENSCI RPF PRE- BAUD RATE SCALER GENERATOR DATA SELECTION ÷ 16 CONTROL ESCI DATA RxD REGISTER SCI_TxD TRANSMIT SHIFT REGISTER BUS CLOCK TXINV ACLK BIT IN SCIACTL ORIE NEIE FEIE PEIE LOOPS ENSCI TRANSMIT CONTROL M LINT WAKE ILTY PEN PTY Freescale Semiconductor TxD ...
Page 155
... Write: See page 173. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 174. Reset: Figure 13-4. ESCI I/O Register Summary MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit PDS2 PDS1 PDS0 PSSB4 ALOST ...
Page 156
... BAUD ÷ 16 ESCI DATA REGISTER DIVIDER SHIFT REGISTER TXINV M PEN PARITY GENERATION PTY T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 13-5. ESCI Transmitter Figure INTERNAL BUS 11-BIT TRANSMIT TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE LINT Freescale Semiconductor 13-4. SCI_TxD ...
Page 157
... Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Functional Description 157 ...
Page 158
... TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 13.4.3 Receiver Figure 13-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 13-4. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 158 NOTE 1. Freescale Semiconductor ...
Page 159
... When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit copy of the eighth bit (bit 7). MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS SCR2 ...
Page 160
... START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 13-7. Receiver Data Sampling Table 13-2. Start Bit Verification Start Bit Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No LSB Noise Flag Freescale Semiconductor ...
Page 161
... A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-3. Data Bit Recovery Data Bit Determination ...
Page 162
... SAMPLES Figure 13-8. Slow Data Figure 13-8, the receiver counts 154 RT cycles at the point when 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 13-8, the receiver counts 170 RT cycles at the point when 170 163 – × 100 = 4.12% ------------------------- - 170 Freescale Semiconductor ...
Page 163
... IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor STOP IDLE OR NEXT CHARACTER DATA SAMPLES Figure 13-9 ...
Page 164
... The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 164 NOTE Freescale Semiconductor ...
Page 165
... ESCI data register, SCDR • ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor (BRK). ESCI During Break Module Interrupts 165 ...
Page 166
... Reset clears the M bit 9-bit ESCI characters 0 = 8-bit ESCI characters MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 166 ENSCI TXINV M WAKE NOTE 2 1 Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 167
... TC bit to generate transmitter CPU interrupt requests – SCRF bit to generate receiver CPU interrupt requests – IDLE bit to generate receiver CPU interrupt requests MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-5. Character Format Selection Character Format Start Bits Data Bits Parity ...
Page 168
... Transmitter enabled 0 = Transmitter disabled Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 168 TCIE SCRIE ILIE NOTE 2 1 Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 169
... R8 — Received Bit 8 When the ESCI is receiving 9-bit characters the read-only ninth bit (bit 8) of the received character received at the same time that the SCDR receives the other 8 bits. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor NOTE NOTE 6 ...
Page 170
... Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0016 Bit 7 Read: SCTE Write: Reset Unimplemented Figure 13-13. ESCI Status Register 1 (SCS1) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 170 SCRF IDLE Bit Freescale Semiconductor ...
Page 171
... The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor I/O Registers 171 ...
Page 172
... READ SCS1 SCRF = 1 SCRF = READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-14. Flag Clearing Sequence BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...
Page 173
... Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register. Do not use read-modify-write instructions on the ESCI data register. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ...
Page 174
... LIN receiver 1 12-bit break detect enabled for LIN receiver 0 13-bit generation enabled for LIN transmitter 1 14-bit generation enabled for LIN transmitter 0 11-bit break detect/13-bit generation enabled for LIN 1 12-bit break detect/14-bit generation enabled for LIN 2 1 Bit 0 SCR2 SCR1 SCR0 Freescale Semiconductor ...
Page 175
... Bit 7 Read: PDS2 Write: Reset: 0 Figure 13-18. ESCI Prescaler Register (SCPSC) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-7. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD Table 13-8. ESCI Baud Rate Selection Baud Rate Divisor (BD) ...
Page 176
... Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/32 = 0.4375 15/32 = 0.46875 Continued on next page Table 13-10. Reset clears Freescale Semiconductor ...
Page 177
... The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Prescaler Divisor Fine Adjust (PDFA) 16/32 = 0.5 17/32 = 0.53125 18/ ...
Page 178
... Freescale Semiconductor ...
Page 179
... Bit time measurement not yet finished ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN Arbiter counter running 0 = Arbiter counter stopped MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor ALOST AFIN ...
Page 180
... ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 180 ARD6 ARD5 ARD4 ARD3 Bit 0 ARD2 ARD1 ARD0 Figure 13-22 RxD on Freescale Semiconductor ...
Page 181
... Figure 13-21. Bit Time Measurement with ACLK = 0 RXD Figure 13-22. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 13-23. Bit Time Measurement with ACLK = 1, Scenario B MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor MEASURED TIME MEASURED TIME MEASURED TIME ESCI Arbiter 181 ...
Page 182
... Enhanced Serial Communications Interface (ESCI) Module MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 182 Freescale Semiconductor ...
Page 183
... IAB IDB PORRST IRST R/W MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 14-1. Signal Name Conventions Description Buffered version of OSC1 from clock generator module (CGM) PLL output PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two) ...
Page 184
... CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE Freescale Semiconductor ...
Page 185
... Reset: Read: Interrupt Status Register 3 $FE06 (INT3) Write: See page 195. Reset: Read: Interrupt Status Register 4 $FE07 (INT4) Write: See page 196. Reset: MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Bit Writing a 0 clears SBSW. POR PIN COP 1 0 ...
Page 186
... Some modules can be programmed to be active in wait mode. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 186 14.6.2 Stop Mode. CGMXCLK Figure 14-3. System Clock Signals Figure 14-3. This clock TO TBM,TIM1,TIM2, ADC, SIM SIMOSCEN SIM COUNTER IT12 TO REST OF CHIP BUS CLOCK IT23 ÷ 2 GENERATORS TO REST OF CHIP Freescale Semiconductor ...
Page 187
... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 14.4 SIM Counter), but an external reset does not. Each of VECT H Figure 14-4 ...
Page 188
... ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR MODRST Figure 14-6. Sources of Internal Reset Table 14-2. Reset Recovery Actual Number of Cycles POR/LVI 4163 (4096 + All others 67 ( the RST pin disables the COP module. VECTOR HIGH while the MCU is in monitor TST Freescale Semiconductor ...
Page 189
... When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor 32 32 CYCLES CYCLES Figure 14-7 ...
Page 190
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 190 Chapter 5 Configuration Register 14.6.2 Stop Mode 14.3.2 Active Resets from Internal Sources shows interrupt recovery timing. Figure 14-10. (CONFIG). for details. The SIM counter is for counter control and Figure 14-8 shows Freescale Semiconductor ...
Page 191
... IAB DUMMY SP IDB DUMMY PC – 1[7:0] PC – 1[15:8] R/W MODULE INTERRUPT I BIT IAB SP – 4 IDB CCR R/W MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor SP – – – – Figure 14-8 Interrupt Entry Timing SP – – – – 1 [7:0] PC – 1 [15:8] OPCODE Figure 14-9 ...
Page 192
... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 192 BREAK YES ? NO NO YES IRQ ? NO YES CGM ? NO OTHER YES ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR SWI YES ? NO RTI YES UNSTACK CPU REGISTERS ? NO EXECUTE INSTRUCTION Figure 14-10. Interrupt Processing SET I BIT Freescale Semiconductor ...
Page 193
... The flags in the interrupt status registers identify maskable interrupt sources. interrupt sources, hardware flag bits, hardware interrupt mask bits, interrupt status register flags, interrupt priority, and exception vectors. The interrupt status registers can be useful for debugging. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor CLI LDA #$FF ...
Page 194
... Freescale Semiconductor ...
Page 195
... Figure 14-14. Interrupt Status Register 3 (INT3) IF22–IF15 — Interrupt Flags 22–15 These flags indicate the presence of an interrupt request from the source shown Interrupt request present interrupt request present MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor IF5 ...
Page 196
... Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 196 Reserved 2 1 Bit 0 0 IF24 IF23 Table 14-3. and Chapter 18 Timer Interface Freescale Semiconductor ...
Page 197
... IDB $A6 $A6 RST CGMXCLK Figure 14-18. Wait Recovery from Internal Reset MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-16. Wait Mode Entry Timing show the timing for WAIT recovery. $6E0B ...
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... MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 198 NOTE Figure 14-19 NOTE STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 14-19. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 shows stop mode entry timing. SAME SAME SAME SAME SP SP – – – 3 Freescale Semiconductor Figure ...
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... Address: $FE01 Bit 7 Read: POR Write: Reset Unimplemented Figure 14-22. SIM Reset Status Register (SRSR) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 Freescale Semiconductor Table 14-4 shows the mapping of these registers. Table 14-4. SIM Registers Register BSR SRSR BFCR ...
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... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5 200 Bit Freescale Semiconductor ...