C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet
C8051F040-GQ
Specifications of C8051F040-GQ
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C8051F040-GQ Summary of contents
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... External 64 kB data memory interface (programma- ble multiplexed or non-multiplexed modes) Digital Peripherals - 8 byte-wide port I/O (C8051F040/2/4/6 tolerant - 4 byte-wide port I/O (C8051F041/3/5/7 tolerant - Bosch Controller Area Network (CAN 2.0B), hard- ware SMBus™ (I2C™ Compatible), SPI™, and ...
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... C8051F040/1/2/3/4/5/6 OTES 2 Rev. 1.4 ...
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... Programmable Digital I/O and Crossbar ........................................................... 29 1.5. Programmable Counter Array ........................................................................... 30 1.6. Controller Area Network.................................................................................... 31 1.7. Serial Ports ....................................................................................................... 31 1.8. 12/10-Bit Analog to Digital Converter................................................................ 32 1.9. 8-Bit Analog to Digital Converter (C8051F040/1/2/3 Only) ............................... 33 1.10.Comparators and DACs ................................................................................... 34 2. Absolute Maximum Ratings .................................................................................. 35 3. Global DC Electrical Characteristic ...................................................................... 36 4. Pinout and Package Definitions............................................................................ 37 5 ...
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... C8051F040/1/2/3/4/5/6/7 7.3.2. Window Detector In Differential Mode.................................................... 102 8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) ......................................... 105 8.1. DAC Output Scheduling.................................................................................. 106 8.1.1. Update Output On-Demand ................................................................... 106 8.1.2. Update Output Based on Timer Overflow .............................................. 106 8.2. DAC Output Scaling/Justification .................................................................... 106 9. Voltage Reference (C8051F040/2/4/6) ................................................................. 113 10. Voltage Reference (C8051F041/3/5/7) ................................................................. 117 11 ...
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... Ports which are not Pinned Out .......................................... 223 17.2.2.Configuring the Output Modes of the Port Pins...................................... 223 17.2.3.Configuring Port Pins as Digital Inputs................................................... 223 17.2.4.Weak Pull-ups ........................................................................................ 223 17.2.5.External Memory Interface ..................................................................... 223 18. Controller Area Network (CAN0) ......................................................................... 229 18.1.Bosch CAN Controller Operation.................................................................... 230 18.1.1.CAN Controller Timing ........................................................................... 231 C8051F040/1/2/3/4/5/6/7 Rev. 1.4 5 ...
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... C8051F040/1/2/3/4/5/6/7 18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 231 18.2.CAN Registers................................................................................................ 233 18.2.1.CAN Controller Protocol Registers......................................................... 233 18.2.2.Message Object Interface Registers ...................................................... 233 18.2.3.Message Handler Registers................................................................... 234 18.2.4.CIP-51 MCU Special Function Registers ............................................... 234 18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to Access CAN Registers .......................................................................... 234 18.2.6.CAN0ADR Autoincrement Feature ........................................................ 234 19 ...
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... Descriptions for PCA0...................................................................... 314 25. JTAG (IEEE 1149.1) .............................................................................................. 319 25.1.Boundary Scan ............................................................................................... 320 25.1.1.EXTEST Instruction................................................................................ 321 25.1.2.SAMPLE Instruction ............................................................................... 321 25.1.3.BYPASS Instruction ............................................................................... 321 25.1.4.IDCODE Instruction................................................................................ 321 25.2.Flash Programming Commands..................................................................... 323 25.3.Debug Support ............................................................................................... 326 Document Change List............................................................................................. 327 Contact Information.................................................................................................. 328 C8051F040/1/2/3/4/5/6/7 Rev. 1.4 7 ...
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... C8051F040/1/2/3/4/5/6 OTES 8 Rev. 1.4 ...
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... List of Figures 1. System Overview Figure 1.1. C8051F040/2 Block Diagram ................................................................. 21 Figure 1.2. C8051F041/3 Block Diagram ................................................................. 22 Figure 1.3. C8051F044/6 Block Diagram ................................................................. 23 Figure 1.4. C8051F045/7 Block Diagram ................................................................. 24 Figure 1.5. Comparison of Peak MCU Execution Speeds ....................................... 25 Figure 1.6. On-Board Clock and Reset .................................................................... 26 Figure 1.7. On-Chip Memory Map............................................................................ 27 Figure 1 ...
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... Figure 7.4. ADC2 Data Word Example .................................................................... 99 Figure 7.5. ADC Window Compare Examples, Single-Ended Mode...................... 101 Figure 7.6. ADC Window Compare Examples, Differential Mode .......................... 102 8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) Figure 8.1. DAC Functional Block Diagram............................................................ 105 9. Voltage Reference (C8051F040/2/4/6) Figure 9.1. Voltage Reference Functional Block Diagram ..................................... 113 10 ...
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... Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 269 Figure 21.4. UART0 Mode 1 Timing Diagram ........................................................ 269 Figure 21.5. UART0 Modes 2 and 3 Timing Diagram ............................................ 271 Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram .............................. 272 Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................... 274 C8051F040/1/2/3/4/5/6/7 Rev. 1.4 11 ...
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... C8051F040/1/2/3/4/5/6/7 22. UART1 Figure 22.1. UART1 Block Diagram ....................................................................... 279 Figure 22.2. UART1 Baud Rate Logic .................................................................... 280 Figure 22.3. UART Interconnect Diagram .............................................................. 281 Figure 22.4. 8-Bit UART Timing Diagram............................................................... 281 Figure 22.5. 9-Bit UART Timing Diagram............................................................... 282 Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................... 283 23 ...
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... ADC (ADC2, C8051F040/1/2/3 Only) Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits) .................. 96 Table 7.2. ADC2 Electrical Characteristics ............................................................ 103 8. DACs, 12-Bit Voltage Mode (C8051F040/1/2/3 Only) Table 8.1. DAC Electrical Characteristics .............................................................. 111 9. Voltage Reference (C8051F040/2/4/6) Table 9.1. Voltage Reference Electrical Characteristics ....................................... 115 10 ...
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... C8051F040/1/2/3/4/5/6/7 18. Controller Area Network (CAN0) Table 18.1. Background System Information ........................................................ 231 Table 18.2. CAN Register Index and Reset Values .............................................. 235 19. System Management BUS / I2C BUS (SMBUS0) Table 19.1. SMB0STA Status Codes and States .................................................. 254 20. Enhanced Serial Peripheral Interface (SPI0) 21. UART0 Table 21.1. UART0 Modes .................................................................................... 268 Table 21 ...
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... SFR Definition 10.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SFR Definition 11.1. CPTnCN: Comparator 0, 1, and 2 Control . . . . . . . . . . . . . . . . . 124 SFR Definition 11.2. CPTnMD: Comparator Mode Selection . . . . . . . . . . . . . . . . . . . 125 SFR Definition 12.1. SFR Page Control Register: SFRPGCN . . . . . . . . . . . . . . . . . . 142 SFR Definition 12.2. SFR Page Register: SFRPAGE . . . . . . . . . . . . . . . . . . . . . . . . . 142 C8051F040/1/2/3/4/5/6/7 Rev. 1.4 15 ...
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... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.3. SFR Next Register: SFRNEXT . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 12.4. SFR Last Register: SFRLAST . . . . . . . . . . . . . . . . . . . . . . . . . . 146 SFR Definition 12.5. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 12.6. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 12.7. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 12 ...
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... SFR Definition 24.2. PCA0MD: PCA0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 SFR Definition 24.3. PCA0CPMn: PCA0 Capture/Compare Mode . . . . . . . . . . . . . . 316 SFR Definition 24.4. PCA0L: PCA0 Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . 317 SFR Definition 24.5. PCA0H: PCA0 Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 317 SFR Definition 24.6. PCA0CPLn: PCA0 Capture Module Low Byte . . . . . . . . . . . . . . 318 C8051F040/1/2/3/4/5/6/7 Rev. 1.4 17 ...
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... C8051F040/1/2/3/4/5/6/7 SFR Definition 24.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . . 318 JTAG Register Definition 25.1. IR: JTAG Instruction Register . . . . . . . . . . . . . . . . . . 319 JTAG Register Definition 25.2. DEVICEID: JTAG Device ID Register . . . . . . . . . . . . 322 JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control Register . . . . . . . . 324 JTAG Register Definition 25.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 325 JTAG Register Definition 25 ...
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... Each MCU is specified for 2 3.6 V operation over the industrial temperature range (–45 to +85 °C). The Port I/Os, /RST, and JTAG pins are tolerant for input signals The C8051F040/2/4/6 are avail- able in a 100-pin TQFP and the C8051F041/3/5/7 are available in a 64-pin TQFP. ...
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... C8051F040/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F040 4352 C8051F041 4352 C8051F042 4352 C8051F043 4352 C8051F044 4352 C8051F045 4352 C8051F046 4352 C8051F047 4352 Rev. 1 100TQFP 64TQFP 100TQFP 64TQFP 3 100TQFP 3 64TQFP 3 100TQFP 3 64TQFP ...
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... ADC AIN0.3 A 100 ksps M Prog (12 or 10- U Gain X Bit) TEMP A SENSOR 8 HVAIN+ HVAMP HVAIN- HVREF HVCAP Figure 1.1. C8051F040/2 Block Diagram C8051F040/1/2/3/4/5/6/7 UART0 8 UART1 SFR Bus SMBus 0 SPI Bus 5 PCA Timers 1 0,1,2,3,4 Memories Port 64 kB 0,1,2,3 Flash &4 Latches C 32x136 CAN ...
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... C8051F040/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND DGND AV+ Analog Power AV+ AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock VREF VREF DAC1 Internal DAC1 (12-Bit) ...
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... AIN0.2 ADC AIN0 Prog 100 ksps U Gain (10-Bit) X TEMP A SENSOR 8 HVAIN+ HVAMP HVAIN- HVREF HVCAP Figure 1.3. C8051F044/6 Block Diagram C8051F040/1/2/3/4/5/6/7 UART0 8 UART1 SFR Bus 0 SMBus SPI Bus 5 PCA Timers 1 0,1,2,3,4 Memories Port 64/32 kB 0,1,2,3 &4 Flash Latches C 32x136 CAN o CANRAM 2 ...
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... C8051F040/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND DGND AV+ Analog Power AV+ AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST V DD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock VREF VREF Internal Oscillator VREFA AIN0.0 AIN0 ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks Silicon Labs (25 MHz clk) Figure 1.5. Comparison of Peak MCU Execution Speeds C8051F040/1/2/3/4/5/6/7 2 2 Microchip Philips ...
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... C8051F040/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F04x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU's program memory consists (C8051F040/1/2/3/4/ (C8051F046/7) of Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip pro- gramming voltage ...
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... MCU is halted, during single stepping breakpoint in order to keep them synchronized with instruc- tion execution. The C8051F040DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F04x MCUs. The development kit includes two target boards and a cable to facilitate evaluating a simple CAN communication network ...
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... Programmable Digital I/O and Crossbar The standard 8051 Ports ( and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 addi- tional 8-bit ports ( and 7) for a total of 64 general-purpose I/O Ports. The Ports behave like the stan- dard 8051 with a few enhancements. Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups" which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power applications ...
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... C8051F040/1/2/3/4/5/6/7 1.5. Programmable Counter Array The C8051F04x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8 ...
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... SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with any other. C8051F040/1/2/3/4/5/6/7 CANRX CAN Controller RX ...
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... INL of ±1LSB. C8051F042/3/4/5/6/7 devices include a 10-bit SAR ADC with similar spec- ifications and configuration options. The ADC0 voltage reference is selected between the DAC0 output and an external VREF pin. On C8051F040/2/4/6 devices, ADC0 has its own dedicated VREF0 input pin; on C8051F041/3/5/7 devices, the ADC0 uses the VREFA input pin and, on the C8051F041/3, shares it with the 8-bit ADC2. The on-chip 15 ppm/° ...
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... Special Function Registers. The ADC2 voltage reference is selected between the analog power supply (AV+) and an external VREF pin. On C8051F040/2 devices, ADC2 has its own dedicated VREF2 input pin; on C8051F041/3 devices, ADC2 shares the VREFA input pin with the 12/10-bit ADC0. User soft- ware may put ADC2 into shutdown mode to save power ...
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... DAC output updates to be forced by a software write or a Timer overflow. The DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the comparators or offsets for the differential inputs of the ADC ...
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... ESD) experienced by these pads may result in impedance degredation of these inputs (HVAIN+ and HVAIN–). For this reason, care should be taken to ensure proper handling and use as typically required to prevent ESD damage to electrostatically sensitive CMOS devices (e.g., static-free workstations, use of grounding straps, over-voltage protection in end-applications, etc.) C8051F040/1/2/3/4/5/6/7 Conditions , AV+, DGND, and Rev. 1.4 ...
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... C8051F040/1/2/3/4/5/6/7 3. Global DC Electrical Characteristic Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Analog Supply Voltage Analog Supply Current Internal REF, ADC, DAC, Com- parators all active Analog Supply Current with Internal REF, ADC, DAC, Com- ...
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... A In ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only) Voltage Reference Input ADC0 Voltage Reference Input ADC2 Voltage Reference Input (C8051F040/2 only DAC Voltage Reference Input (C8051F040/2 only ADC0 Input Channel 0 (See ADC0 Specification for complete description ADC0 Input Channel 1 (See ADC0 Specification for complete description) ...
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... A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specifi- cation for complete description). (C8051F040/1/2/3 only) D I/O Port 0.0. See Port Input/Output section for complete description. D I/O Port 0.1. See Port Input/Output section for complete description. ...
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... P3.5/AD5/ P3.6/AD6/ P3.7/AD7/ P4.0 98 C8051F040/1/2/3/4/5/6/7 Type Description A In Port 1.4. See Port Input/Output section for complete description Port 1.5. See Port Input/Output section for complete description Port 1.6. See Port Input/Output section for complete description Port 1.7. See Port Input/Output section for complete description. ...
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... C8051F040/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F040/2/4/6 F041/3/5/7 P4.1 97 P4.2 96 P4.3 95 P4.4 94 P4.5/ALE 93 P4.6/RD 92 P4.7/WR 91 P5.0/A8 88 P5.1/A9 87 P5.2/A10 86 P5.3/A11 85 P5.4/A12 84 P5.5/A13 83 P5.6/A14 82 P5.7/A15 81 P6.0/A8m/A0 80 P6.1/A9m/A1 79 P6.2/A10m/A2 78 P6.3/A11m/A3 77 P6.4/A12m/A4 76 P6.5/A13m/A5 75 P6.6/A14m/A6 74 P6.7/A15m/A7 73 P7.0/AD0/ Type Description D I/O Port 4.1. See Port Input/Output section for complete description. ...
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... P7.6/AD6/D6 66 P7.7/AD7/D7 65 C8051F040/1/2/3/4/5/6/7 Type Description D I/O Port 7.1. See Port Input/Output section for complete description. D I/O Port 7.2. See Port Input/Output section for complete description. D I/O Port 7.3. See Port Input/Output section for complete description. D I/O Port 7.4. See Port Input/Output section for complete description. ...
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... AGND 10 AV+ 11 VREF 12 AGND 13 AV+ 14 VREFD 15 VREF0 16 VREF2 17 AIN0.0 18 AIN0.1 19 AIN0.2 20 AIN0.3 21 HVCAP 22 HVREF 23 HVAIN+ 24 HVAIN- 25 Figure 4.1. TQFP-100 Pinout Diagram 42 C8051F040/2/4/6 Rev. 1.4 75 P6.5/A13m/A5 74 P6.6/A14m/A6 73 P6.7/A15m/A7 72 P7.0/AD0/D0 71 P7.1/AD1/D1 70 P7.2/AD2/D2 69 P7.3/AD3/D3 68 P7.4/AD4/D4 67 P7.5/AD5/D5 66 P7.6/AD6/D6 65 P7.7/AD7/D7 64 VDD 63 DGND 62 P0.0 61 P0.1 60 P0 ...
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... PIN 1 DESIGNATOR Figure 4.2. TQFP-100 Package Drawing C8051F040/1/2/3/4/5/6 Rev. 1.4 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14. 0.45 0.60 0.75 43 ...
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... C8051F040/1/2/3/4/5/6/7 CANRX 1 CANTX 2 AV+ 3 AGND 4 AGND 5 AV+ 6 VREF 7 VREFA 8 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 HVCAP 13 HVREF 14 HVAIN+ 15 HVAIN- 16 Figure 4.3. TQFP-64 Pinout Diagram 44 C8051F041/3/5/7 Rev. 1.4 48 P0.7/WR 47 P3.0/AD0/D0 46 P3.1/AD1/D1 45 P3.2/AD2/D2 44 P3.3/AD3/D3 43 P3.4/AD4/D4 42 P3.5/AD5/D5 41 VDD 40 DGND 39 P3.6/AD6/D6 38 P3.7/AD7/D7 37 P2.0/A8m/A0 36 P2.1/A9m/A1 35 P2.2/A10m/A2 34 P2.3/A11m/A3 33 P2.4/A12m/A4 ...
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... PIN 1 DESIGNATOR Figure 4.4. TQFP-64 Package Drawing C8051F040/1/2/3/4/5/6 Rev. 1.4 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10. 0.45 0.6 0.75 45 ...
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... C8051F040/1/2/3/4/5/6 OTES 46 Rev. 1.4 ...
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... ADC (ADC0, C8051F040/1 Only) The ADC0 subsystem for the C8051F040/1 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-regis- ter ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
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... C8051F040/1/2/3/4/5/6/7 5.1.1. Analog Input Configuration The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (See “17.1.5. Configuring Port 1, 2, and 3 Pins as Analog Inputs” on page Amplifier, and an on-chip temperature sensor as shown in Figure 5.2. AIN0.0 AIN0.1 AIN0.2 AIN0.3 ...
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... SFR Definition 5.2. AMX0SL: AMUX0 Channel Select Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per Table 5.1. C8051F040/1/2/3/4/5/6/7 R R/W R/W R/W - PORT3IC HVDA2C AIN23IC Bit4 Bit3 Bit2 Bit1 R R/W R/W ...
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... C8051F040/1/2/3/4/5/6/7 Table 5.1. AMUX Selection Chart (AMX0AD3–0 and AMX0CF3–0 bits) 0000 0001 0000 AIN0.0 AIN0.1 +(AIN0.0) 0001 -(AIN0.1) 0010 AIN0.0 AIN0.1 +(AIN0.0) 0011 -(AIN0.1) 0100 AIN0.0 AIN0.1 +(AIN0.0) 0101 -(AIN0.1) 0110 AIN0.0 AIN0.1 +(AIN0.0) 0111 -(AIN0.1) 1000 AIN0.0 AIN0.1 +(AIN0 ...
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... P3.0 is not selected as an analog input to the AMUX. 1: P3.0 is enabled as an analog input to the AMUX. Note:Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd numbered and even numbered pins that are selected simultaneously are shorted together as “wired-OR”. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W ...
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... C8051F040/1/2/3/4/5/6/7 5.2. High Voltage Difference Amplifier The High Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be suitable for input to ADC0. The input signal to the HVDA may be below AGND to –60 volts, and as high as +60 volts, making the device suitable for both single and dual supply applications ...
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... HVGAIN3:HVGAIN0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 C8051F040/1/2/3/4/5/6/7 R R/W R/W R/W - HVGAIN3 HVGAIN2 HVGAIN1 HVGAIN0 00000000 Bit4 Bit3 Bit2 Bit1 HVDA Gain 0.05 0.1 0.125 0.2 0.25 0.4 ...
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... C8051F040/1/2/3/4/5/6/7 5.3. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys- tem clock divided by the value held in the ADC0SC bits of register ADC0CF. 5.3.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following: • ...
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... Track Or Convert B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0STM[1:0]=00, 01, 11 SAR Clocks Low Power ADC0TM=1 Track or Convert 1 2 SAR Clocks Track or ADC0TM=0 Convert Figure 5.4. 12-Bit ADC Track and Conversion Example Timing C8051F040/1/2/3/4/5/6 Track Convert Convert ...
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... C8051F040/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 5.5 shows the equivalent ADC0 input circuits for both differential and Single-ended modes ...
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... Figure 5.6. Temperature Sensor Transfer Function C8051F040/1/2/3/4/5/6 0.00286(TEMP ) + 0.776 TEMP C for PGA Gain = 1 50 100 Rev. 1.4 (Celsius) 57 ...
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... C8051F040/1/2/3/4/5/6/7 SFR Definition 5.5. ADC0CF: ADC0 Configuration Register R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK SAR clock ...
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... ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bit0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W AD0WINT Bit4 ...
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... C8051F040/1/2/3/4/5/6/7 SFR Definition 5.7. ADC0H: ADC0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits of the 12-bit ADC0 Data Word. ...
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... For AD0LJST = 0: Gain × × -------------- - n Code = Vin 2 ; ‘n’ for Single-Ended; ‘n’=11 for Differential. VREF Figure 5.7. ADC0 Data Word Example C8051F040/1/2/3/4/5/6/7 ADC0H:ADC0L (AD0LJST = 1) 0xFFF0 0x8000 0x7FF0 0x0000 ADC0H:ADC0L (AD0LJST = 1) 0x7FF0 0x4000 0x0010 0x0000 0xFFF0 0xC000 0x8000 Rev ...
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... C8051F040/1/2/3/4/5/6/7 5.4. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
Page 63
... ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x0200 and > 0x0100. Figure 5.8. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 ...
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... C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x07FF AD0WINT not affected 0x0101 REF x (256/2048) 0x0100 ADC0LTH:ADC0LTL 0x00FF AD0WINT=1 0x0000 REF x (-1/2048) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE AD0WINT not affected 0xF800 -REF Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF ...
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... An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x2000 and > 0x1000. Figure 5.10. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) ...
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... C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x7FF0 AD0WINT not affected 0x1010 REF x (256/2048) 0x1000 ADC0LTH:ADC0LTL 0x0FF0 AD0WINT=1 0x0000 REF x (-1/2048) 0xFFF0 ADC0GTH:ADC0GTL 0xFFE0 AD0WINT not affected 0x8000 -REF Given: AMX0SL = 0x00, AMX0CF = 0x01, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFF0 ...
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... Notes 1, 2 (Temp = 0 °C) Power Specifications Power Supply Current (AV+ sup- Operating Mode, 100 ksps plied to ADC) Power Supply Rejection Notes: 1. Represents one standard deviation from the mean. 2. Includes ADC offset, gain, and linearity variations. C8051F040/1/2/3/4/5/6/7 Conditions Min Typ 12 — — — — ...
Page 68
... C8051F040/1/2/3/4/5/6/7 Table 5.3. High Voltage Difference Amplifier Electrical Characteristics V = 3.0 V, AV Parameter Analog Inputs Differential range Common Mode Range Analog Output Output Voltage Range DC Performance Common Mode Rejection Ratio Offset Voltage Noise Nonlinearity Dynamic Performance Small Signal Bandwidth Small Signal Bandwidth ...
Page 69
... AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configu- ration register, ADC0CF (SFR Definition 6.5). The PGA can be software-programmed for gains of 0. 16. Gain defaults to unity on reset. C8051F040/1/2/3/4/5/6/7 Section “9. Voltage Reference (C8051F040/2/4/6)” on page 113 ADC0LTH ADC0LTL AV+ ...
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... C8051F040/1/2/3/4/5/6/7 6.1.1. Analog Input Configuration The analog multiplexer routes signals from external analog input pins, Port 3 I/O pins (programmed to be analog inputs), a High Voltage Difference Amplifier, and an on-chip temperature sensor as shown in Figure 6.2. AIN0.0 AIN0.1 AIN0.2 AIN0.3 PAIN0EN P3.6 PAIN2EN PAIN4EN P3 ...
Page 71
... SFR Definition 6.2. AMX0SL: AMUX0 Channel Select Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per Table 6.1. C8051F040/1/2/3/4/5/6/7 R R/W R/W R/W - PORT3IC HVDA2C AIN23IC Bit4 Bit3 Bit2 Bit1 R R/W R/W ...
Page 72
... C8051F040/1/2/3/4/5/6/7 Table 6.1. AMUX Selection Chart (AMX0AD3-0 and AMX0CF3-0 bits) 0000 0001 0000 AIN0.0 AIN0.1 +(AIN0.0) 0001 -(AIN0.1) 0010 AIN0.0 AIN0.1 +(AIN0.0) 0011 -(AIN0.1) 0100 AIN0.0 AIN0.1 +(AIN0.0) 0101 -(AIN0.1) 0110 AIN0.0 AIN0.1 +(AIN0.0) 0111 -(AIN0.1) 1000 AIN0.0 AIN0.1 +(AIN0.0) 1001 -(AIN0 ...
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... P3.0 is not selected as an analog input to the AMUX. 1: P3.0 is enabled as an analog input to the AMUX. NOTE: Any number of Port 3 pins may be selected simultaneously inputs to the AMUX. Odd num- bered and even numbered pins that are selected simultaneously are shorted together as “wired-OR”. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
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... C8051F040/1/2/3/4/5/6/7 6.2. High Voltage Difference Amplifier The High Voltage Difference Amplifier (HVDA) can be used to measure high differential voltages peak-to-peak, reject high common-mode voltages up to ±60 V, and condition the signal voltage range to be suitable for input to ADC0. The input signal to the HVDA may be below AGND to -60 volts, and as high as +60 volts, making the device suitable for both single and dual supply applications ...
Page 75
... HVGAIN3:HVGAIN0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 C8051F040/1/2/3/4/5/6/7 R R/W R/W R/W - HVGAIN3 HVGAIN2 HVGAIN1 HVGAIN0 00000000 Bit4 Bit3 Bit2 Bit1 HVDA Gain 0.05 0.1 0.125 0.2 0.25 0.4 ...
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... C8051F040/1/2/3/4/5/6/7 6.3. ADC Modes of Operation ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys- tem clock divided by the value held in the ADC0SC bits of register ADC0CF. 6.3.1. Starting a Conversion A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following: • ...
Page 77
... Track Or Convert B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to AD0BUSY (AD0STM[1:0]=00, 01, 11 SAR Clocks Low Power ADC0TM=1 Track or Convert 1 2 SAR Clocks Track or ADC0TM=0 Convert Figure 6.4. 10-Bit ADC Track and Conversion Example Timing C8051F040/1/2/3/4/5/6 Track Convert Convert ...
Page 78
... C8051F040/1/2/3/4/5/6/7 6.3.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0 MUX resistance, the ADC0 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 6.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes ...
Page 79
... Figure 6.6. Temperature Sensor Transfer Function C8051F040/1/2/3/4/5/6 0.00286(TEMP ) + 0.776 TEMP C for PGA Gain = 1 50 100 Rev. 1.4 (Celsius) 79 ...
Page 80
... C8051F040/1/2/3/4/5/6/7 SFR Definition 6.5. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK SAR clock ...
Page 81
... ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bit0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W AD0WINT Bit4 ...
Page 82
... C8051F040/1/2/3/4/5/6/7 SFR Definition 6.7. ADC0H: ADC0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-2 are the sign extension of Bit 1. Bits 0 and 1 are the upper 2 bits of the 10-bit ADC0 Data Word. ...
Page 83
... ADLJST = 0: Gain × × -------------- - n Code = Vin 2 ; ‘n’ for Single-Ended; ‘n’=9 for Differential. VREF Figure 6.7. ADC0 Data Word Example C8051F040/1/2/3/4/5/6/7 ADC0H:ADC0L (ADLJST = 1) 0xFFC0 0x8000 0x7FC0 0x0000 ADC0H:ADC0L (ADLJST = 1) 0x7FC0 0x4000 0x0040 0x0000 0xFFC0 0xC000 0x8000 Rev ...
Page 84
... C8051F040/1/2/3/4/5/6/7 6.4. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
Page 85
... ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0200 and > 0x0100. Given: Figure 6.8. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 ...
Page 86
... C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x01FF AD0WINT not affected 0x0101 REF x (256/512) 0x0100 ADC0LTH:ADC0LTL 0x00FF AD0WINT=1 0x0000 REF x (-1/512) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE AD0WINT not affected 0xFE00 -REF Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF. ...
Page 87
... An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x8000 and > 0x4000. Given: Figure 6.10. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 ...
Page 88
... C8051F040/1/2/3/4/5/6/7 Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x7FC0 AD0WINT not affected 0x4040 REF x (256/512) 0x4000 ADC0LTH:ADC0LTL 0x3FC0 AD0WINT=1 0x0000 REF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL 0xFF80 AD0WINT not affected 0x8000 -REF Given: AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0x4000, ADC0GTH:ADC0GTL = 0xFFC0. ...
Page 89
... Temp = 0 °C Offset Power Specifications Power Supply Current Operating Mode, 100 ksps (AV+ supplied to ADC) Power Supply Rejection Notes: 1. Represents one standard deviation from the mean. 2. Includes ADC offset, gain, and linearity variations. C8051F040/1/2/3/4/5/6/7 Conditions Min Typ 10 — — — — — ...
Page 90
... C8051F040/1/2/3/4/5/6/7 Table 6.3. High Voltage Difference Amplifier Electrical Characteristics V = 3.0 V, AV Parameter Analog Inputs Differential range Common Mode Range Analog Output Output Voltage Range DC Performance Common Mode Rejection Ratio Offset Voltage Noise Nonlinearity Dynamic Performance Small Signal Bandwidth Small Signal Bandwidth ...
Page 91
... ADC (ADC2, C8051F040/1/2/3 Only) The ADC2 subsystem for the C8051F040/1/2/3 consists of an 8-channel, configurable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-register ADC with inte- grated track-and-hold (see block diagram in Figure 7.1). The AMUX2, PGA2, and Data Conversion Modes, are all configurable under software control via the Special Function Registers shown in Figure 7 ...
Page 92
... C8051F040/1/2/3/4/5/6/7 7.2. ADC2 Modes of Operation ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock divided version of the system clock, determined by the AD2SC bits in the ADC2CF register (system clock divided by (AD2SC + 1) for 0 ≤ AD2SC ≤ 31). The maximum ADC2 conversion clock is 7.5 MHz. ...
Page 93
... Write '1' to AD2BUSY, Timer 3 Overflow, Timer 2 Overflow, Write '1' to AD0BUSY (AD2CM[2:0]=000, 001, 011, 0xx) SAR2 Clocks Low Power AD2TM=1 or Convert SAR2 Clocks Track or AD2TM=0 Convert Figure 7.2. ADC2 Track and Conversion Example Timing C8051F040/1/2/3/4/5/6 Track Convert Low Power Mode Convert ...
Page 94
... C8051F040/1/2/3/4/5/6/7 7.2.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit. ...
Page 95
... SFR Definition 7.2. AMX2SL: AMUX2 Channel Select Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care Bits2-0: AMX2AD2-0: AMX2 Address Bits 000-111b: ADC Inputs selected per Table 7.1. C8051F040/1/2/3/4/5/6/7 R R/W R/W R/W - PIN67IC PIN45IC PIN23IC Bit4 Bit3 Bit2 Bit1 R R ...
Page 96
... C8051F040/1/2/3/4/5/6/7 Table 7.1. AMUX Selection Chart (AMX2AD2-0 and AMX2CF3-0 bits) 000 001 0000 P1.0 P1.1 +(P1.0) -(P1.0) 0001 -(P1.1) +(P1.1) 0010 P1.0 P1.1 +(P1.0) -(P1.0) 0011 -(P1.1) +(P1.1) 0100 P1.0 P1.1 +(P1.0) -(P1.0) 0101 -(P1.1) +(P1.1) 0110 P1.0 P1.1 +(P1.0) -(P1.0) 0111 -(P1 ...
Page 97
... CLK SAR2 *Note: AD2SC is the rounded-up result. Bit2: UNUSED. Read = 0b. Write = don’t care. Bits1-0: AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA) 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 C8051F040/1/2/3/4/5/6/7 R/W R/W R AD2SC1 AD2SC0 - AMP2GN1 AMP2GN0 11111000 Bit4 Bit3 Bit2 SYSCLK ---------------------------- – ...
Page 98
... C8051F040/1/2/3/4/5/6/7 SFR Definition 7.4. ADC2CN: ADC2 Control R/W R/W R/W AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 Bit7 Bit6 Bit5 Bit7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 Enabled. ADC2 is active and ready for data conversions. Bit6: AD2TM: ADC2 Track Mode Bit. ...
Page 99
... Example: ADC2 Data Word Conversion Map, AIN1.0 Input (AMX2SL = 0x00) AIN1.0-AGND (Volts) VREF * (255/256) VREF / 2 VREF * (127/256) 0 Gain × -------------- - Code = Vin VREF Figure 7.4. ADC2 Data Word Example C8051F040/1/2/3/4/5/6/7 R/W R/W R/W Bit4 Bit3 Bit2 ADC2 0xFF 0x80 0x7F 0x00 × 256 Rev. 1.4 R/W ...
Page 100
... C8051F040/1/2/3/4/5/6/7 7.3. ADC2 Programmable Window Detector The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
Page 101
... REF x (32/256) 0x20 ADC2LT 0x1F 0x11 REF x (16/256) 0x10 ADC2GT 0x0F AD2WINT not affected 0x00 0 Figure 7.5. ADC Window Compare Examples, Single-Ended Mode C8051F040/1/2/3/4/5/6/7 ADC2 Input Voltage (P1.x - GND) REF x (255/256) 0xFF 0x21 REF x (32/256) 0x20 0x1F AD2WINT=1 0x11 REF x (16/256) 0x10 ...
Page 102
... C8051F040/1/2/3/4/5/6/7 7.3.2. Window Detector In Differential Mode Figure 7.6 shows two example window comparisons for differential mode, with ADC2LT = 0x10 (+16d) and ADC2GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x (127/128) and are represented as 8-bit 2s complement signed integers. In the left example, an AD2WINT interrupt will be generated if the ADC2 conversion word (ADC2L) is within the range defined by ADC2GT and ADC2LT (if 0xFF (– ...
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... Track/Hold Acquisition Time Throughput Rate Analog Inputs Input Voltage Range Single-ended Common Mode Range Input Capacitance Power Specifications Power Supply Current Operating Mode, 500 ksps (AV+ supplied to ADC2) Power Supply Rejection C8051F040/1/2/3/4/5/6/7 Conditions Min Typ 8 — — — — — 0.5±0.3 — ...
Page 104
... C8051F040/1/2/3/4/5/6 OTES 104 Rev. 1.4 ...
Page 105
... The voltage reference for each DAC is supplied at the VREFD pin (C8051F040/2 devices) or the VREF pin (C8051F041/3 devices). Note that the VREF pin on C8051F041/3 devices may be driven by the internal voltage reference or an external source. If the internal voltage refer- ence is used it must be enabled in order for the DAC outputs to be valid. See ence (C8051F040/2/4/6)” ...
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... C8051F040/1/2/3/4/5/6/7 8.1. DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” write to the high- byte of the DAC0 data register (DAC0H) ...
Page 107
... Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. SFR Definition 8.2. DAC0L: DAC0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
Page 108
... C8051F040/1/2/3/4/5/6/7 SFR Definition 8.3. DAC0CN: DAC0 Control R DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
Page 109
... Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. SFR Definition 8.5. DAC1L: DAC1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
Page 110
... C8051F040/1/2/3/4/5/6/7 SFR Definition 8.6. DAC1CN: DAC1 Control R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
Page 111
... Output Voltage Swing Startup Time Analog Outputs I L Load Regulation 0xFFF Power Consumption (each DAC) Power Supply Current (AV+ Data Word = 0x7FF supplied to DAC) C8051F040/1/2/3/4/5/6/7 = 2.40 V (REFBE = 0), No Output Load unless otherwise specified. Conditions = 0.01mA to 0 code Rev. 1.4 Min Typ Max Units 12 bits — ...
Page 112
... C8051F040/1/2/3/4/5/6 OTES 112 Rev. 1.4 ...
Page 113
... The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage ref- erence input pins allow each ADC and the two DACs (C8051F040/2 only) to reference an external voltage reference or the on-chip voltage reference output. ADC0 may also reference the DAC0 output internally, and ADC2 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 9 ...
Page 114
... UNUSED. Read = 000b; Write = don’t care. Bit4: AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREF0 pin. 1: ADC0 voltage reference from DAC0 output (C8051F040/2 only). Bit3: AD2VRS: ADC2 Voltage Reference Select (C8051F040/2 only). 0: ADC2 voltage reference from VREF2 pin. ...
Page 115
... VREF Turn-on Time 2 0.1 µF ceramic bypass VREF Turn-on Time 3 no bypass cap Reference Buffer Power Supply Current Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current C8051F040/1/2/3/4/5/6/7 Conditions Min Typ 2.36 2.43 0.5 140 1.00 Rev. 1.4 Max Units 2 ...
Page 116
... C8051F040/1/2/3/4/5/6 OTES 116 Rev. 1.4 ...
Page 117
... VDD External R1 Voltage Reference Circuit 4.7µF Recommended Bypass Capacitors Figure 10.1. Voltage Reference Functional Block Diagram C8051F040/1/2/3/4/5/6/7 for C8051F041 devices that feature a 12-bit ADC, or PGA” on page 69 for C8051F043/5/7 devices that feature a 10-bit REF0CN (C8051F041/3 only) AV VREFA ...
Page 118
... C8051F040/1/2/3/4/5/6/7 SFR Definition 10.1. REF0CN: Reference Control R/W R/W R Bit7 Bit6 Bit5 Bits7-5: UNUSED. Read = 000b; Write = don’t care. Bit4: AD0VRS: ADC0 Voltage Reference Select 0: ADC0 voltage reference from VREFA pin. 1: ADC0 voltage reference from DAC0 output (C8051F041/3 only). Bit3: AD2VRS: ADC2 Voltage Reference Select (C8051F041/3 only) ...
Page 119
... VREF Turn-on Time 2 0.1 µF ceramic bypass VREF Turn-on Time 3 no bypass cap Reference Buffer Power Supply Current Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current C8051F040/1/2/3/4/5/6/7 Conditions Min Typ 2.36 2.43 — — — 0.5 — ...
Page 120
... C8051F040/1/2/3/4/5/6 OTES 120 Rev. 1.4 ...
Page 121
... CP0 + P2.6 CP0 - P2.7 CP1 + P2.2 CP1 - P2.3 CP2 + P2.4 CP2 - P2.5 Figure 11.1. Comparator Functional Block Diagram C8051F040/1/2/3/4/5/6/7 Section “17.1.5. Configuring Port 1, 2, and 3 Pins as Ana- 169). Section “17.1.1. Crossbar Pin Assignment ) + 0.25 V without damage or upset. DD VDD CPn + + SET SET D Q ...
Page 122
... C8051F040/1/2/3/4/5/6/7 CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 11.2. Comparator Hysteresis Plot The hysteresis of the Comparator is software-programmable via its Comparator Control register (CPT- nCN). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage ...
Page 123
... Inputs” on page 209). The inputs for Comparator are on Port 2 as follows: Comparator Input CP0+ CP0– CP1+ CP1– CP2+ CP2– C8051F040/1/2/3/4/5/6/7 Section “17.1.3. Configuring Port Pins as Digi- Port PIN P2.6 P2.7 P2.2 P2.3 P2.4 P2.5 Rev. 1.4 ...
Page 124
... C8051F040/1/2/3/4/5/6/7 SFR Definition 11.1. CPTnCN: Comparator 0, 1, and 2 Control R/W R R/W CPnEN CPnOUT CPnRIF Bit7 Bit6 Bit5 SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88 SFR Pages: CPT0CN:page 1;CPT1CN:page 2; CPT2CN:page 3 Bit7: CPnEN: Comparator Enable Bit. (Please see note below.) 0: Comparator Disabled. ...
Page 125
... Bits3-2: UNUSED. Read = 00b, Write = don’t care. Bits1-0: CPnMD1-CPnMD0: Comparator Mode Select These bits select the response time for the Comparator. Mode CPnMD1 CPnMD0 C8051F040/1/2/3/4/5/6/7 R CPnFIE - - CPnMD1 CPnMD0 00000010 Bit4 Bit3 Bit2 CPn Typical Response Time 0 Fastest Response Time 1 — ...
Page 126
... C8051F040/1/2/3/4/5/6/7 Table 11.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter CPn+ – CPn– = 100 mV Response Time, Mode 0 CPn+ – CPn– CPn+ – CPn– = 100 mV Response Time, Mode 1 CPn+ – CPn– CPn+ – CPn– = 100 mV ...
Page 127
... PSW PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 12.1. CIP-51 Block Diagram C8051F040/1/2/3/4/5/6/7 Section 23), two full-duplex UARTs (see description in Section 25), and interfaces directly with the MCUs' - Extended Interrupt Handler - Reset Input - Power Management Modes ...
Page 128
... C8051F040/1/2/3/4/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 129
... SUBB A, #data Subtract immediate from A with borrow INC A Increment A INC Rn Increment register INC direct Increment direct byte INC @Ri Increment indirect RAM DEC A Decrement A C8051F040/1/2/3/4/5/6/7 181). The External Memory Interface provides a fast for details. Arithmetic Operations Rev. 1.4 Section Clock Bytes Cycles ...
Page 130
... C8051F040/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct ...
Page 131
... Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR JZ rel Jump if A equals zero C8051F040/1/2/3/4/5/6/7 Boolean Manipulation Program Branching Rev. 1.4 Clock Bytes Cycles ...
Page 132
... C8051F040/1/2/3/4/5/6/7 Table 12.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal Compare immediate to Register and jump if not ...
Page 133
... Byte Sectors) 0x0000 12.2.1. Program Memory The CIP-51 has a 64k byte program memory space. The MCU implements 64 kB (C8051F040/1/2/3/4/5) and 32 kB (C8051F046/7) of this program memory space as in-system re-programmed Flash memory, organized in a contiguous block from addresses 0x0000 to 0xFFFF (C8051F040/1/2/3/4/5) and 0x0000 to 0x7FFF (C8051F046/7) ...
Page 134
... C8051F040/1/2/3/4/5/6/7 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 135
... CPU to return to a different SFR Page upon execution of the RETI instruc- tion (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of the stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack. C8051F040/1/2/3/4/5/6/7 Rev. 1.4 135 ...
Page 136
... C8051F040/1/2/3/4/5/6/7 Interrupt Logic Figure 12.3. SFR Page Stack Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). This function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless dis- abled in software ...
Page 137
... Page Stack Example The following is an example of a C8051F040 device that shows the operation of the SFR Page Stack dur- ing interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR Page 0x0F) ...
Page 138
... C8051F040/1/2/3/4/5/6/7 While CIP-51 executes in-line code (writing values to Port 5 in this example), an ADC2 Window Compara- tor Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to access ADC2’ ...
Page 139
... SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 12.6 below. SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 12.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR C8051F040/1/2/3/4/5/6/7 SFR Page 0x00 Automatically pushed on stack in SFRPAGE on PCA interrupt 0x00 SFRPAGE (PCA) ...
Page 140
... C8051F040/1/2/3/4/5/6/7 On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC2 ISR can continue to access SFR’ ...
Page 141
... RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See SFR Definition 12.1. C8051F040/1/2/3/4/5/6/7 SFR Page 0x02 Automatically ...
Page 142
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.1. SFR Page Control Register: SFRPGCN Bit7 Bit6 Bit5 Bits7-1: Reserved. Bit0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt the C8051 Core will vector to the specified interrupt service routine and auto- matically switch the SFR page to the corresponding peripheral or function’s SFR page. This bit is used to control this autopaging function ...
Page 143
... SFRPAGE SFR to have this SFR page value upon a return from interrupt. Read: Returns the value of the SFR page contained in the second byte of the SFR stack. This is the value that will go to the SFR Page register upon a return from interrupt. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 144
... C8051F040/1/2/3/4/5/6/7 Table 12.2. Special Function Register (SFR) Memory Map 0(8) 1(9) 2( SPI0CN PCA0L PCA0H CAN0CN (ALL PAGES) ADC0CN PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 ADC2CN E8 P6 PCA0CPL5 PCA0CPH5 ACC E0 (ALL PAGES) XBR0 XBR1 PCA0CN PCA0MD PCA0CPM0 CAN0DATL CAN0DATH CAN0ADR D8 P5 REF0CN ...
Page 145
... TL0 TCON CPT0CN CPT0MD 88 CPT1MD CPT1CN CPT2MD CPT2CN OSCICN P0 SP DPL 80 (ALL PAGES) (ALL PAGES) (ALL PAGES) 0(8) 1(9) 2(A) C8051F040/1/2/3/4/5/6/7 3(B) 4(C) 5(D) P1MDIN EMI0CF P0MDOUT P1MDOUT SPI0DAT SPI0CKR P4MDOUT P5MDOUT TL1 TH0 TH1 OSCICL OSCXCN DPH SFRPAGE SFRNEXT (ALL PAGES) ...
Page 146
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.4. SFR Last Register: SFRLAST R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SFR page context is retained upon interrupts/return from interrupts byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third entry. The SFR stack bytes may be used alter the context in the SFR Page Stack, and will not cause the stack to ‘ ...
Page 147
... DAC0L 3 0xD4 1 DAC1CN 3 0xD3 1 DAC1H C8051F040/1/2/3/4/5/6/7 Description ADC0 Configuration ADC0 Control ADC0 Greater-Than High ADC0 Greater-Than Low ADC0 Data Word High ADC0 Data Word Low ADC0 Less-Than High ADC0 Less-Than Low ADC2 Data Word ADC2 Analog Multiplexer Configuration ADC2 Control ...
Page 148
... C8051F040/1/2/3/4/5/6/7 Table 12.3. Special Function Registers (Continued) SFR’s are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page 3 0xD2 1 DAC1L DPH 0x83 All Pages Data Pointer High DPL 0x82 All Pages Data Pointer Low EIE1 0xE6 ...
Page 149
... SMB0DAT 0xC2 0 SMB0STA 0xC1 0 SP 0x81 All Pages Stack Pointer C8051F040/1/2/3/4/5/6/7 Description PCA Capture 4 High PCA Capture 5 High PCA Capture 0 Low PCA Capture 1 Low PCA Capture 2 Low PCA Capture 3 Low PCA Capture 4 Low PCA Capture 5 Low PCA Module 0 Mode Register ...
Page 150
... Notes: 1. Refers to a register in the C8051F040 only. 2. Refers to a register in the C8051F041 only. 3. Refers to a register in C8051F040/1/2/3 only. 4. Refers to a register in the C8051F040/2/4/6 only. 5. Refers to a register in the C8051F041/3/5/7 only. 150 Description SPI Configuration SPI Clock Rate Control ...
Page 151
... SFR Definition 12.7. DPH: Data Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W ...
Page 152
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.8. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 153
... This register is the accumulator for arithmetic operations. SFR Definition 12.10 Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W ACC.4 ACC.3 ACC.2 ACC.1 Bit4 Bit3 Bit2 R/W R/W R/W B ...
Page 154
... C8051F040/1/2/3/4/5/6/7 12.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt- pending flag(s) located in an SFR ...
Page 155
... Timer 2 0x002B Serial Peripheral 0x0033 Interface SMBus Interface 0x003B ADC0 Window 0x0043 Comparator Programmable Counter 0x004B Array Comparator 0 0x0053 Comparator 1 0x005B Comparator 2 0x0063 C8051F040/1/2/3/4/5/6/7 Priority Pending Flag Order Top None N/A N/A 0 IE0 (TCON. TF0 (TCON. IE1 (TCON. TF1 (TCON.7) Y RI0 (SCON0.0) ...
Page 156
... C8051F040/1/2/3/4/5/6/7 Table 12.4. Interrupt Summary (Continued) Interrupt Interrupt Source Vector Timer 3 0x0073 ADC0 End of Conversion 0x007B Timer 4 0x0083 ADC2 Window 0x0093 Comparator ADC2 End of Conversion 0x008B CAN Interrupt 0x009B UART1 0x00A3 156 Priority Pending Flag Order 14 TF3 (TMR3CN.7) ADC0INT 15 Y (ADC0CN.5) 16 TF4 (T4CON ...
Page 157
... The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051F040/1/2/3/4/5/6/7 Rev. 1.4 157 ...
Page 158
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.11. IE: Interrupt Enable R/W R/W R/W EA IEGF0 ET2 Bit7 Bit6 Bit5 Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ...
Page 159
... Timer 0 interrupt set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 priority set to low priority level. 1: External Interrupt 0 set to high priority level. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W PS0 PT1 ...
Page 160
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.13. EIE1: Extended Interrupt Enable 1 R/W R/W R/W CP2IE CP1IE Bit7 Bit6 Bit5 Bit7: Reserved. Read = 0b, Write = don’t care. Bit6: CP2IE: Enable Comparator (CP2) Interrupt. This bit sets the masking of the CP2 interrupt. 0: Disable CP2 interrupts. 1: Enable interrupt requests generated by the CP2IF flag. ...
Page 161
... Disable CAN Controller Interrupt. 1: Enable interrupt requests generated by the CAN Controller. Bit4: EADC2: Enable ADC2 End Of Conversion Interrupt (C8051F040/1/2/3 only). This bit sets the masking of the ADC2 End of Conversion interrupt. 0: Disable ADC2 End of Conversion interrupt. 1: Enable interrupt requests generated by the ADC2 End of Conversion Interrupt. ...
Page 162
... C8051F040/1/2/3/4/5/6/7 SFR Definition 12.15. EIP1: Extended Interrupt Priority 1 R/W R/W R/W - PCP2 PCP1 Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: PCP2: Comparator2 (CP2) Interrupt Priority Control. This bit sets the priority of the CP2 interrupt. 0: CP2 interrupt set to low priority level. 1: CP2 interrupt set to high priority level. ...
Page 163
... CAN Interrupt set to low priority level. 1: CAN Interrupt set to high priority level. Bit4: PADC2: ADC2 End Of Conversion Interrupt Priority Control (C8051F040/1/2/3 only). This bit sets the priority of the ADC2 End of Conversion interrupt. 0: ADC2 End of Conversion interrupt set to low level. 1: ADC2 End of Conversion interrupt set to low level. ...
Page 164
... C8051F040/1/2/3/4/5/6/7 12.17. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped ...
Page 165
... Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’ effect. 1: CIP-51 forced into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) C8051F040/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 166
... C8051F040/1/2/3/4/5/6 OTES 166 Rev. 1.4 ...
Page 167
... Comparator0 CP0 CP0- Internal Clock Generator XTAL1 OSC XTAL2 C8051F040/1/2/3/4/5/6/7 Monitor resets, the /RST pin is driven low until the end of the V “14. Oscillators” on page “13.7. Watchdog Timer Reset” on page 169). Once the system clock V DD Supply Monitor Supply + ...
Page 168
... C8051F040/1/2/3/4/5/6/7 13.1. Power-on Reset The C8051F04x family incorporates a power supply monitor that holds the MCU in the reset state until V rises above the V level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for RST the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end ...
Page 169
... The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in SFR Definition 13.1. C8051F040/1/2/3/4/5/6/7 “14. Oscillators” on page 175) enables the Missing Clock Detector. “11. ...
Page 170
... C8051F040/1/2/3/4/5/6/7 13.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and reset as a result of any system reset. ...
Page 171
... Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Bits2-0: Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 ...
Page 172
... C8051F040/1/2/3/4/5/6/7 SFR Definition 13.2. RSTSRC: Reset Source R R/W R/W - CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR0 is not a reset source. 1: CNVSTR0 is a reset source (active low). Read: 0: Source of prior reset was not CNVSTR0. ...
Page 173
... POR Threshold ( RST Minimum /RST Low Time to Generate a System Reset Reset Time Delay RST rising edge after V V RST Missing Clock Detector Time from last system clock to Timeout reset initiation C8051F040/1/2/3/4/5/6/7 Conditions Min = 8 1.0 1.0 2.40 crosses DD threshold 100 Rev ...
Page 174
... C8051F040/1/2/3/4/5/6 OTES 174 Rev. 1.4 ...
Page 175
... Electrical specifications for the precision internal oscillator are given in Table 14.1 on page 177. The pro- grammed internal oscillator frequency must not exceed 25 MHz. The system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN. C8051F040/1/2/3/4/5/6/7 OSCICL OSCICN ...
Page 176
... C8051F040/1/2/3/4/5/6/7 SFR Definition 14.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: OSCICL: Internal Oscillator Calibration Register This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. The reset value is factory calibrated to generate an inter- nal oscillator frequency of 24 ...
Page 177
... SFR Definition 14.3. CLKSEL: Oscillator Clock Selection Bit7 Bit6 Bit5 Bits7-1: Reserved. Bit0: CLKSL: System Clock Source Select Bit. 0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in OSCICN. 1: SYSCLK derived from the External Oscillator circuit. C8051F040/1/2/3/4/5/6/7 Conditions Min 24 — Bit4 ...
Page 178
... C8051F040/1/2/3/4/5/6/7 SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: External Oscillator Mode Bits. ...
Page 179
... Figure 14.2. 32.768 kHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as C8051F040/1/2/3/4/5/6/7 XTAL1 Ω XTAL2 Rev ...
Page 180
... C8051F040/1/2/3/4/5/6/7 short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 14.5. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout ...
Page 181
... Flash Memory The C8051F04x family includes 128 (C8051F040/1/2/3/4/ 128 (C8051F046/7) of on- chip, reprogrammable Flash memory for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software using the MOVX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. Flash write and erase opera- tions are automatically timed by hardware for proper execution ...
Page 182
... Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller. A set of security lock bytes stored at 0xFDFE and 0xFDFF (C8051F040/1/2/3/4/5) and at 0x7FFE and 0x7FFF (C8051F046/7) protect the Flash program memory from being read or altered across the JTAG interface ...
Page 183
... MOVX and MOVC instructions to read, write, or erase Flash locations below this address. Any attempts to read locations below this limit will return the value 0x00. Figure 15.1. Flash Program Memory Map and Security Bytes C8051F040/1/2/3/4/5/6/7 SFLE = 0 C8051F040/1/2/3/4/5 Scratchpad Memory Reserved 0xFE00 Read Lock Byte ...
Page 184
... This erasure can only be performed via JTAG non-security byte in the 0xFBFF-0xFDFF (C8051F040/1/2/3/4/5) or 0x7DFF-0x7FFF (C8051F046/7) page is addressed during the JTAG era- sure, only that page (including the security bytes) will be erased. ...
Page 185
... JTAG interface. 6. The page containing the security bytes may be read from or written to. Pages of Flash can be locked from JTAG access by writing to the security bytes. 7. The Reserved Area cannot be read from, written to, or erased at any time. C8051F040/1/2/3/4/5/6/7 Rev. 1.4 185 ...
Page 186
... C8051F040/1/2/3/4/5/6/7 SFR Definition 15.1. FLACL: Flash Access Limit R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: FLACL: Flash Access Limit. This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL ...
Page 187
... Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The location must be erased prior to writing data. 0: Write to Flash program memory disabled. MOVX write operations target External RAM. 1: Write to Flash program memory enabled. MOVX write operations target Flash memory. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 188
... C8051F040/1/2/3/4/5/6 OTES 188 Rev. 1.4 ...
Page 189
... MOV EMI0CN, #12h MOV R0, #34h MOVX a, @R0 C8051F040/1/2/3/4/5/6/7 for details. The MOVX instruction ; load DPTR with 16-bit address to read (0x1234) ; load contents of 0x1234 into accumulator A ; load high byte of address into EMI0CN ; load low byte of address into R0 (or R1) ; load contents of 0x1234 into accumulator A Rev ...
Page 190
... The External Memory Interface can appear on Ports and 0 (C8051F04x devices Ports and 4 (C8051F040/2/4/6 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports are selected, the EMIFLE bit (XBR2.1) must be set to a ‘1’ so that the Crossbar will skip over P0 ...
Page 191
... The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. 0x00: 0x0000 to 0x00FF 0x01: 0x0100 to 0x01FF ... 0xFE: 0xFE00 to 0xFEFF 0xFF: 0xFF00 to 0xFFFF C8051F040/1/2/3/4/5/6/7 R/W R/W R/W PGSEL4 PGSEL3 PGSEL2 PGSEL1 ...
Page 192
... C8051F040/1/2/3/4/5/6/7 SFR Definition 16.2. EMI0CF: External Memory Configuration R/W R/W R PRTSEL Bit7 Bit6 Bit5 Bits7-6: Unused. Read = 00b. Write = don’t care. Bit5: PRTSEL: EMIF Port Select. 0: EMIF active on P0-P3. 1: EMIF active on P4-P7. Bit4: EMD2: EMIF Multiplex Mode Select. 0: EMIF operates in multiplexed address/data mode. ...
Page 193
... Bus controls the state of the AD[7:0] port at the time /RD or /WR is asserted. See Section “16.6.2. Multiplexed Mode” on page 201 A[15:8] E ALE AD[7:0] ADDRESS/DATA BUS /WR /RD Figure 16.1. Multiplexed Configuration Example C8051F040/1/2/3/4/5/6/7 for more information. ADDRESS BUS 74HC373 (Optional) 8 Rev. 1.4 A[15:8] A[7:0] ...
Page 194
... C8051F040/1/2/3/4/5/6/7 16.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non- multiplexed Configuration is shown in Figure 16.2. See page 198 for more information about Non-multiplexed operation. A[15: D[7:0] F /WR /RD Figure 16.2. Non-multiplexed Configuration Example 194 Section “ ...
Page 195
... On-Chip XRAM On-Chip XRAM Off-Chip Memory (No Bank Select) On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM 0x0000 Figure 16.3. EMIF Operating Modes C8051F040/1/2/3/4/5/6/7 Section “16.6. Timing” on page EMI0CF[3: EMI0CF[3: 0xFFFF 0xFFFF Off-Chip Memory (Bank Select) On-Chip XRAM 0x0000 0x0000 Rev ...
Page 196
... C8051F040/1/2/3/4/5/6/7 16.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off- chip space. • Effective addresses below the 4k boundary will access on-chip XRAM space. • Effective addresses above the 4k boundary will access off-chip space. ...
Page 197
... SYSCLK cycles. Bits1-0: EAH1-0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. C8051F040/1/2/3/4/5/6/7 R/W R/W R/W EWR2 EWR1 EWR0 EAH1 ...
Page 198
... C8051F040/1/2/3/4/5/6/7 16.6.1. Non-multiplexed Mode 16.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.4. Non-multiplexed 16-bit MOVX Timing 198 Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH ...
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... P0.6/P4.6 ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.5. Non-multiplexed 8-bit MOVX without Bank Select Timing C8051F040/1/2/3/4/5/6/7 Nonmuxed 8-bit WRITE without Bank Select P1/P5 EMIF ADDRESS (8 LSBs) from EMIF WRITE DATA T WDS T T ACS ACW Nonmuxed 8-bit READ without Bank Select ...
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... C8051F040/1/2/3/4/5/6/7 16.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Figure 16.6. Non-multiplexed 8-bit MOVX with Bank Select Timing 200 Nonmuxed 8-bit WRITE with Bank Select ...