C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 168

• Manufacturer Part Number: C8051F040-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 13-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 64
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Data Rom Size: 64 KB
• A/d Bit Size: 12 bit
• A/d Channels Available: 13
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1204

C8051F040/1/2/3/4/5/6/7
13.7.1. Enable/Reset WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-
tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.
13.7.2. Disable WDT
Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment
illustrates disabling the WDT:
The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is
ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes.
13.7.3. Disable WDT Lockout
Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored
until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always
intending to use the watchdog should write 0xFF to WDTCN in the initialization code.
13.7.4. Setting WDT Interval
WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:
For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be
logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads
111b after a system reset.
168
4
3
CLR
MOV
MOV
SETB
+
WDTCN 2 0
EA
WDTCN,#0DEh
WDTCN,#0ADh
EA

–


T
sysclk
; disable all interrupts
; disable software watchdog timer
; re-enable interrupts
; where T
sysclk
is the system clock period.
Rev. 1.5