C8051F061-GQ Silicon Laboratories Inc, C8051F061-GQ Datasheet - Page 13
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C8051F061-GQ
Manufacturer Part Number
C8051F061-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
2-ch x 16-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1215
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F061-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F061-GQR
Manufacturer:
SILICON
Quantity:
2 100
Company:
Part Number:
C8051F061-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
19. Controller Area Network (CAN0, C8051F060/1/2/3) ........................................... 225
20. System Management BUS / I2C BUS (SMBUS0)................................................ 235
21. Enhanced Serial Peripheral Interface (SPI0)...................................................... 251
Figure 18.5. XBR0: Port I/O Crossbar Register 0................................................... 210
Figure 18.6. XBR1: Port I/O Crossbar Register 1................................................... 211
Figure 18.7. XBR2: Port I/O Crossbar Register 2................................................... 212
Figure 18.8. XBR3: Port I/O Crossbar Register 3................................................... 213
Figure 18.9. P0: Port0 Data Register ..................................................................... 214
Figure 18.10. P0MDOUT: Port0 Output Mode Register ......................................... 214
Figure 18.11. P1: Port1 Data Register ................................................................... 215
Figure 18.12. P1MDIN: Port1 Input Mode Register................................................ 215
Figure 18.13. P1MDOUT: Port1 Output Mode Register ......................................... 216
Figure 18.14. P2: Port2 Data Register ................................................................... 216
Figure 18.15. P2MDIN: Port2 Input Mode Register................................................ 217
Figure 18.16. P2MDOUT: Port2 Output Mode Register ......................................... 217
Figure 18.17. P3: Port3 Data Register ................................................................... 218
Figure 18.18. P3MDOUT: Port3 Output Mode Register ......................................... 218
Figure 18.19. P4: Port4 Data Register ................................................................... 221
Figure 18.20. P4MDOUT: Port4 Output Mode Register ......................................... 221
Figure 18.21. P5: Port5 Data Register ................................................................... 222
Figure 18.22. P5MDOUT: Port5 Output Mode Register ......................................... 222
Figure 18.23. P6: Port6 Data Register ................................................................... 223
Figure 18.24. P6MDOUT: Port6 Output Mode Register ......................................... 223
Figure 18.25. P7: Port7 Data Register ................................................................... 224
Figure 18.26. P7MDOUT: Port7 Output Mode Register ......................................... 224
Figure 19.1. CAN Controller Diagram..................................................................... 226
Figure 19.2. Typical CAN Bus Configuration.......................................................... 226
Figure 19.3. CAN0DATH: CAN Data Access Register High Byte .......................... 231
Figure 19.4. CAN0DATL: CAN Data Access Register Low Byte............................ 231
Figure 19.5. CAN0ADR: CAN Address Index Register .......................................... 232
Figure 19.6. CAN0CN: CAN Control Register ........................................................ 232
Figure 19.7. CAN0TST: CAN Test Register ........................................................... 233
Figure 19.8. CAN0STA: CAN Status Register........................................................ 233
Figure 20.1. SMBus0 Block Diagram ..................................................................... 235
Figure 20.2. Typical SMBus Configuration ............................................................. 236
Figure 20.3. SMBus Transaction ............................................................................ 237
Figure 20.4. Typical Master Transmitter Sequence................................................ 238
Figure 20.5. Typical Master Receiver Sequence.................................................... 238
Figure 20.6. Typical Slave Transmitter Sequence.................................................. 239
Figure 20.7. Typical Slave Receiver Sequence...................................................... 240
Figure 20.8. SMB0CN: SMBus0 Control Register.................................................. 243
Figure 20.9. SMB0CR: SMBus0 Clock Rate Register............................................ 244
Figure 20.10. SMB0DAT: SMBus0 Data Register.................................................. 245
Figure 20.11. SMB0ADR: SMBus0 Address Register............................................ 246
Figure 20.12. SMB0STA: SMBus0 Status Register ............................................... 247
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
13