C8051F061-GQ Silicon Laboratories Inc, C8051F061-GQ Datasheet - Page 51
C8051F061-GQ
Manufacturer Part Number
C8051F061-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
2-ch x 16-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1215
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Manufacturer
Quantity
Price
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Part Number:
C8051F061-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F061-GQR
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5.
The ADC subsystem for the C8051F060/1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi-
mation-register ADCs with integrated track-and-hold, a Programmable Window Detector, and a DMA inter-
face (see block diagrams in Figure 5.1 and Figure 5.2). The ADCs can be configured as two separate,
single-ended ADCs, or as a differential pair. The Data Conversion Modes, Window Detector, and DMA
interface are all configurable under software control via the Special Function Registers shown in Figure 5.1
and Figure 5.2. The voltage references used by ADC0 and ADC1 are selected as described in
The ADCs and their respective track-and-hold circuitry can be independently enabled or disabled with the
Special Function Registers. Either ADC can be enabled by setting the ADnEN bit in the ADC’s Control reg-
ister (ADCnCN) to logic 1. The ADCs are in low power shutdown when these bits are logic 0.
(DC, -0.2 to 0.6 V)
(DC, -0.2 to 0.6 V)
AIN0G
AIN1G
AIN0
AIN1
16-Bit ADCs (ADC0 and ADC1)
SYSCLK
SYSCLK
Figure 5.1. 16-Bit ADC0 and ADC1 Control Path Diagram
ADC0CF
ADC1CF
ADC0
ADC1
16-Bit
16-Bit
SAR
SAR
AV+
AV+
Rev. 1.2
ADC0CN
ADC1CN
AD0EN
AD1EN
C8051F060/1/2/3/4/5/6/7
Start Conversion
Start Conversion
ADC0 Data Bus
ADC1 Data Bus
16
16
000
010
100
110
xx1
00
01
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AD1BUSY (W)
Timer 3 Overflow
CNVSTR1
Timer 2 Overflow
AD0BUSY (W)
Section
51
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