C8051F061-GQ Silicon Laboratories Inc, C8051F061-GQ Datasheet - Page 168
C8051F061-GQ
Manufacturer Part Number
C8051F061-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
2-ch x 16-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1215
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C8051F060/1/2/3/4/5/6/7
168
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
Reserved.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write:
Read:
C0RSEF: Comparator0 Reset Enable and Flag.
Write:
Read:
SWRSF: Software Reset Force and Flag.
Write:
Read:
WDTRSF: Watchdog Timer Reset Flag.
MCDRSF: Missing Clock Detector Flag.
Write:
Read:
PORSF: Power-On Reset Flag.
Write:
this bit can be written to select or de-select the VDD monitor as a reset source.
Important: At power-on, the VDD monitor is enabled/disabled using the external VDD
monitor enable pin (MONEN). The PORSF bit does not disable or enable the VDD monitor
circuit. It simply selects the VDD monitor as a reset source.
Read:
reset or a VDD monitor reset. In either case, data memory should be considered indeterminate
following the reset.
Note: When this flag is read as '1', all other reset flags are indeterminate.
PINRSF: HW Pin Reset Flag.
Write:
Read:
CNVRSEF
R/W
Bit6
0: CNVSTR2 is not a reset source.
1: CNVSTR2 is a reset source (active low).
0: Source of prior reset was not CNVSTR2.
1: Source of prior reset was CNVSTR2.
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
0: No effect.
1: Forces an internal reset. /RST pin is not effected.
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.
0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
If the VDD monitor circuitry is enabled (by tying the MONEN pin to a logic high state),
0: De-select the VDD monitor as a reset source.
1: Select the VDD monitor as a reset source.
This bit is set whenever a power-on reset occurs. This may be due to a true power-on
0: Source of last reset was not a power-on or VDD monitor reset.
1: Source of last reset was a power-on or VDD monitor reset.
0: No effect.
1: Forces a Power-On Reset. /RST is driven low.
0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.
detected.
C0RSEF
R/W
Bit5
Figure 14.4. RSTSRC: Reset Source Register
SWRSEF
R/W
Bit4
WDTRSF
Rev. 1.2
Bit3
R
MCDRSF
R/W
Bit2
PORSF
R/W
Bit1
SFR Address:
PINRSF
SFR Page:
R/W
Bit0
0xEF
0
Reset Value
00000000
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