MCF53012CQT240 Freescale Semiconductor, MCF53012CQT240 Datasheet - Page 15

• Manufacturer Part Number: MCF53012CQT240
• Description: MCU 32BIT COLDFIRE EMAC 208LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5301xr

Specifications of MCF53012CQT240

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 61
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Cache
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Processor Series: MCF5301x
• Core: ColdFire V3
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: UART, I2C, SPI, SSI, Ethernet
• Maximum Clock Frequency: 20 MHz to 400 MHz
• Number Of Programmable I/os: 61
• Number Of Timers: 8
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M53015EVB, M53017KIT, M53017MOD
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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AVSS_SPKR_HDST
VDD_OSC_A_PLL
AVSS_SPKR_HP
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
The edge port 1 signals are the primary functions on two sets of pins (IRQ1FECn and IRQ1DEBUGn). If an IRQ1 function is configured on
both pins, the IRQ1FECn pin takes priority. The corresponding IRQ1DEBUGn pin is disconnected internally from the edge port 1 module.
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
AVDD_CODEC
VSTBY_SRAM
VSS_CODEC
Signal Name
AVDD_SPKR
VSTBY_RTC
VDD_USBO
VDD_USBH
VDD_EPM
VDD_RTC
SD_VDD
Freescale Semiconductor
EVDD
TEST
IVDD
VSS
GPIO
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Table 6. MCF5301x Signal Information and Muxing (continued)
Preliminary—Subject to Change Without Notice
Alternate 1
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MCF5301x Data Sheet, Rev. 5
Power Supplies
Alternate 2
Test
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D
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I
Pin Assignments and Reset States
EVDD
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16, 44, 69, 77, 128,
51, 54, 57, 74, 126,
138, 168, 180, 192,
48, 52, 53, 56, 68,
9, 24, 26, 40, 47,
7, 102, 116, 156,
8, 15, 25, 39, 45,
73, 76, 101, 117,
MCF53010
MCF53011
MCF53012
MCF53013
163, 181, 208
208 LQFP
169, 193
139, 195
146
147
194
46
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80
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96
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83
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E9, F8, F9, H5, H6, H11,
L5-7, L10-12, M5-7, M12
E5, E6, E10-12, F6, F7,
A1, A16, G7-10, H7-10,
J7-10, K7-10, T1, T16
H12, J6, J11, L8, L9
256 MAPBGA
F5, G6, G11, G12,
J12, K6, K11, K12,
MCF53014
MCF53015
MCF53016
MCF53017
F10, F11
N10
F12
T10
M4
M9
N8
E7
E8
T8
L2
L4
T6
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