MCF53012CQT240 Freescale Semiconductor, MCF53012CQT240 Datasheet - Page 60
![MCU 32BIT COLDFIRE EMAC 208LQFP](/photos/37/62/376255/lqfp-112_sml.jpg)
MCF53012CQT240
Manufacturer Part Number
MCF53012CQT240
Description
MCU 32BIT COLDFIRE EMAC 208LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5301xr
Datasheet
1.MCF53010CQT240.pdf
(62 pages)
Specifications of MCF53012CQT240
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, PWM, WDT
Number Of I /o
61
Program Memory Size
16KB (16K x 8)
Program Memory Type
Cache
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Processor Series
MCF5301x
Core
ColdFire V3
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
UART, I2C, SPI, SSI, Ethernet
Maximum Clock Frequency
20 MHz to 400 MHz
Number Of Programmable I/os
61
Number Of Timers
8
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M53015EVB, M53017KIT, M53017MOD
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Preliminary Electrical Characteristics
5.22
Table 40
60
lists specifications for the debug AC timing parameters shown in
Debug AC Timing Specifications
TCLK
TMS
TDO
TDO
TDO
TDI
TRST
1
TCLK
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
Num
DSCLK input relative to the rising edge of PSTCLK.
D4
D0
D1
D2
D3
D5
D6
1
PSTCLK cycle time
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
DSCLK-to-DSO hold
DSCLK cycle time
BKPT assertion time
V
IL
Preliminary—Subject to Change Without Notice
Table 40. Debug AC Timing Specification
Characteristic
Figure 40. Test Access Port Timing
J11
J12
J11
J13
MCF5301x Data Sheet, Rev. 5
Figure 41. TRST Timing
J14
J9
Input Data Valid
Min
1.5
1.5
—
1
4
5
1
Figure
Output Data Valid
Output Data Valid
V
42.
IH
Max
1.5
3.0
J10
—
—
—
—
—
PSTCLK
PSTCLK
PSTCLK
PSTCLK
Units
t
SYS
ns
ns
Freescale Semiconductor