DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 214
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block
transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
For operation in normal mode and block transfer mode, see section 7.5, Operation.
Bits 10 to 7—Reserved: Can be read or written to. Write 0 to these bits.
Bit 6—Destination Address Increment/Decrement (DAID)
Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address
register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Bit 4—Reserved: Can be read or written to. Write 0 to this bit.
Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The
factors that can be specified differ between normal mode and block transfer mode.
Rev.6.00 Oct.28.2004 page 184 of 1016
REJ09B0138-0600H
Normal Mode
Bit 12
BLKDIR
0
1
Bit 6
DAID
0
1
Bit 3
DTF3
0
1
Bit 2
DTF2
0
1
Bit 11
BLKE
0
1
0
1
Bit 5
DAIDE
0
1
0
1
Bit 1
DTF1
0
1
0
1
Description
Transfer in normal mode
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
Description
MARB is fixed
MARB is incremented after a data transfer
MARB is fixed
MARB is decremented after a data transfer
When DTSZ = 0, MARB is incremented by 1 after a transfer
When DTSZ = 1, MARB is incremented by 2 after a transfer
When DTSZ = 0, MARB is decremented by 1 after a transfer
When DTSZ = 1, MARB is decremented by 2 after a transfer
Bit 0
DTF0
0
1
0
1
0
1
Description
—
—
Activated by DREQ pin falling edge input
Activated by DREQ pin low-level input
—
Auto-request (cycle steal)
Auto-request (burst)
—
(Initial value)
(Initial value)
(Initial value)
: Don't care
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