DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 439
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-count in the T
TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow.
Multiplexing of I/O Pins: In the H8S/2357 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the
TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin
with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a
multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled
before entering module stop mode.
ø
Address
Write signal
TCNT
TCFV flag
Figure 10-57 Contention between TCNT Write and Overflow
H'FFFF
Prohibited
TCNT write cycle
T
TCNT address
1
T
2
M
TCNT write data
Rev.6.00 Oct.28.2004 page 409 of 1016
REJ09B0138-0600H
2
state of a
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