DF2398TE20V Renesas Electronics America, DF2398TE20V Datasheet - Page 310
![IC H8S MCU FLASH 256K 120TQFP](/photos/12/21/122170/df2398te20v_sml.jpg)
DF2398TE20V
Manufacturer Part Number
DF2398TE20V
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
HD64F2398TE20V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 310 of 1049
- Download datasheet (5Mb)
P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. As the PPG, TPU, and 8-bit timer are initialized by a manual reset*, the pin states
are determined by the P2DDR and P2DR specifications.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 2 Data Register (P2DR)
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2
P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port 2 Register (PORT2)
Note: * Determined by state of pins P2
PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2
pins (P2
If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while
P2DDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and
P2DR are initialized. PORT2 retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 280 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Bit
Initial value :
R/W
7
to P2
:
:
:
:
0
) must always be performed on P2DR.
P27DR
R/W
P27
—*
7
0
7
R
P26DR
R/W
P26
—*
6
0
6
R
7
P25DR
to P2
R/W
P25
—*
5
0
5
R
0
.
P24DR
R/W
P24
—*
4
0
4
R
P23DR
R/W
P23
—*
3
0
3
R
P22DR
R/W
P22
—*
2
0
2
R
P21DR
R/W
P21
—*
1
0
1
R
7
to P2
P20DR
R/W
P20
—*
0
0
0
R
0
).
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