MC912DG128ACPVER Freescale Semiconductor, MC912DG128ACPVER Datasheet - Page 175
![IC MCU 16BIT 8K FLASH 112-LQFP](/photos/12/21/122171/mc912dg128acpver_sml.jpg)
MC912DG128ACPVER
Manufacturer Part Number
MC912DG128ACPVER
Description
IC MCU 16BIT 8K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DG128ACPVER
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 8 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC912DG128ACPVERTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 175 of 478
- Download datasheet (4Mb)
12.6.14 PLL Register Descriptions
SYNR — Synthesizer Register
REFDV — Reference Divider Register
CGTFLG — Clock Generator Test Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
RESET:
RESET:
TSTOUT7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
TSTOUT6
6
0
0
6
0
0
6
0
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Always reads zero, except in test modes.
Freescale Semiconductor, Inc.
For More Information On This Product,
TSTOUT5
SYN5
5
0
5
0
0
5
0
Go to: www.freescale.com
TSTOUT4
SYN4
Clock Functions
4
0
4
0
0
4
0
TSTOUT3
SYN3
3
0
3
0
0
3
0
Limp-Home and Fast STOP Recovery modes
TSTOUT2
REFDV2
SYN2
2
0
2
0
2
0
TSTOUT1
REFDV1
SYN1
1
0
1
0
1
0
TSTOUT0
REFDV0
SYN0
Bit 0
Bit 0
Bit 0
0
0
0
Clock Functions
Technical Data
$003A
$0038
$0039
175
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