MC912DG128ACPVER Freescale Semiconductor, MC912DG128ACPVER Datasheet - Page 401
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MC912DG128ACPVER
Manufacturer Part Number
MC912DG128ACPVER
Description
IC MCU 16BIT 8K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DG128ACPVER
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC912D
Core
HC12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
69
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 8 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC912DG128ACPVERTR
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
STM
Quantity:
1 244
Company:
Part Number:
MC912DG128ACPVER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.4.3 BDM Commands
MC68HC912DT128A — Rev 4.0
MOTOROLA
Figure 20-3
MC68HC912DT128A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target MC68HC912DT128A finishes it.
Since the target wants the host to receive a logic zero, it drives the
BKGD pin low for 13 BDMCLK cycles, then briefly drives it high to speed
up the rising edge. The host samples the bit level about ten cycles after
starting the bit time.
The BDM command set consists of two types: hardware and firmware.
Hardware commands allow target system memory to be read or
written.Target system memory includes all memory that is accessible by
the CPU12 including EEPROM, on-chip I/O and control registers, and
external memory that is connected to the target HC12 MCU.Hardware
commands are implemented in hardware logic and do not require the
HC12 MCU to be in BDM mode for execution.The control logic watches
the CPU12 buses to find a free bus cycle to execute the command so the
background access does not disturb the running application programs. If
a free cycle is not found within 128 BDMCLK cycles, the CPU12 is
momentarily frozen so the control logic can steal a cycle.Commands
implemented in BDM control logic are listed in
Freescale Semiconductor, Inc.
For More Information On This Product,
shows the host receiving a logic zero from the target
Go to: www.freescale.com
Development Support
Table
Background Debug Mode
20-2.
Development Support
Technical Data
401
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