HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 337
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS
Quantity:
450
Company:
Part Number:
HD64F7144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7144F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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6.3.6
Description: Clears the Dz operand. When conditions are specified for DCT and DCF, the
instruction is executed when those conditions are TRUE. When they are FALSE, the instruction is
not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The Z bit of the DSR register is set to 1. The N, V, and GT bits are
cleared to 0. If conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the
conditions were true and the instruction was executed.
Operation:
Format
PCLR Dz
DCT PCLR
Dz
DCF PCLR
Dz
/* PCLR Dz
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* ALU Destination assignment */
switch (zzzz) { /* Dz Operand selection bit (zzzz) */
if(DSP_UNCONDITIONAL_UPDATE) { /* unconditional operation */
[if cc] PCLR (Clear): DSP Arithmetic Operation Instruction
break;
break;
Abstract
H'00000000 Dz
if DC = 1, H'00000000 Dz
if 0, nop
if DC = 0, H'00000000 Dz
if 1, nop
case 0x5: A1 = 0x0;
case 0x7: A0 = 0x0;
case 0x8: X0 = 0x0;
A1G = 0x0;
A0G = 0x0;
*/
Code
111110**********
100011010000zzzz
111110**********
100011100000zzzz
111110**********
100011110000zzzz
Rev. 5.00 Jun 30, 2004 page 321 of 512
1
1
1
Cycle
Section 6 Instruction Descriptions
DC Bit
Update
—
—
REJ09B0171-0500O
SH-1
—
—
—
Instructions
Applicable
SH-2
—
—
—
SH-
DSP
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