HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 429
![IC SUPERH MCU FLASH 256K 112QFP](/photos/12/21/122194/hd64f7144f50v_sml.jpg)
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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HD64F7144F50V
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7.2
Contention occurs in four cases. When it occurs, the slot splits and requires at least two cycles.
1. Contention between instruction fetch (IF) and memory access (MA)
2. Contention when the previous instruction’s destination register is used
3. Multiplier access contention
4. Contention between memory stores (MA) and either DSP operations or memory loads
7.2.1
Basic Operation when IF and MA Are in Contention (Common): The IF and MA stages both
access memory, so they cannot operate simultaneously. When the IF and MA stages both try to
access memory within the same slot, the slot splits as shown in figure 7.6. When there is a WB, it
is executed immediately after the MA ends.
(WB/DSP)
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Contention
Contention between Instruction Fetch (IF) and Memory Access (MA)
When MA and IF are in contention, the following occurs:
Figure 7.6 Operation when IF and MA Are in Contention
IF
IF
A
A
ID
ID
IF
IF
B
B
EX
EX
ID
ID
IF
IF
C
C
MA
MA
EX
ID
—
—
IF
D
D
W/D
W/D
MA
EX
EX
ID
ID
IF
IF
E
W/D
MA
EX
ID
—
—
F
E
W/D
EX
EX
Rev. 5.00 Jun 30, 2004 page 413 of 512
ID
G
IF
MA of instruction 1 and IF of
instruction 4 contend at D
MA of instruction 2 and IF of
instruction 5 contend at E
EX
ID
F
EX
Section 7 Pipeline Operation
G
REJ09B0171-0500O
: Slot
: Slot
Split at D
Split at E
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