HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 72

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
4.7.5
When the S bit of the SR register is set to 1, the overflow prevention function is engaged for the
ALU fixed decimal point arithmetic operation executed by the DSP unit. When the operation
result overflows, the maximum (positive) or minimum (negative) value is stored.
4.8
ALU integer operations are basically 24-bit operations on the top word (the top 16 bits, or bits 16
through 31) and 8 guard bits. In ALU integer operations, the bottom word of the source operand
(the bottom 16 bits, or bits 0–15) is ignored and the bottom word of the destination operand is
cleared with zeros. When the source operand has no guard bits, the sign bit is extended to fill the
guard bits. When the destination operand has no guard bits, the top word of the operation result
(not including the guard bits) are stored in the top word of the destination register.
Integer operations are basically the same as ALU fixed decimal point arithmetic operations. There
are only two types of integer operation instructions, increment and decrement, which change the
second operand by +1 or –1. 16 bits of integer data (word data) is loaded to the DSP register and
stored in the top word. The operation is performed using the top word in the DSP register. When
there are guard bits, they are valid as well. These operations are executed in the DSP stage (the last
stage) of the pipeline.
Whenever an ALU integer arithmetic operation is executed, the DSR register’s DC, N, Z, V, and
GT bits are basically updated by the operation result. This is the same as for ALU fixed decimal
point operations.
For conditional instructions, condition bits and flags are not updated even when the specified
condition is achieved and the instruction executed. For unconditional instructions, the bits are
always updated according to the operation result. Figure 4.11 shows the ALU integer operation
flowchart.
Rev. 5.00 Jun 30, 2004 page 56 of 512
REJ09B0171-0500O
Overflow Prevention Function (Saturation Operation)
ALU Integer Operations