DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 198
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 198 of 341
- Download datasheet (2Mb)
Section 2 Instruction Descriptions
2.2.52 (6)
ROTR (ROTate Right)
Operation
ERd (right rotation)
Assembly-Language Format
ROTR.L #2, ERd
Operand Size
Longword
Description
This instruction rotates the bits in a 32-bit register ERd (destination operand) two bits to the right.
The least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 31 and
30), and bit 1 is also copied to the carry flag.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 182 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
ROTR (L)
Mnemonic
ROTR.L
ERd
MSB
b31
Operands
b30
#2, ERd
. . . .
1st byte
1
3
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 1.
2nd byte
F
Instruction Format
cleared to 0.
cleared to 0.
—
I
b1
0 erd
UI H
—
LSB
b0
—
3rd byte
—
U
C
N
4th byte
Z
V
0
States
No. of
C
Rotate
1
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