DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 23
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 23 of 341
- Download datasheet (2Mb)
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto
the stack in exception handling, they are stored as shown in figure 1.3. When EXR is invalid, it is
not pushed onto the stack. For details, see the relevant hardware manual.
(2) Advanced Mode
In advanced mode the data address space is larger than for the H8/300H CPU.
Address Space: The 4-Gbyte maximum address space provides linear access to a maximum
16 Mbytes of program code and maximum 4 Gbytes of data.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.
Instruction Set: All instructions and addressing modes can be used.
SP
Notes: 1.
(a) Subroutine Branch
2.
3.
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored on return.
(16 bits)
Figure 1.3 Stack Structure in Normal Mode
PC
(SP
SP
*2
Rev. 4.00 Feb 24, 2006 page 7 of 322
)
(b) Exception Handling
Reserved
(16 bits)
CCR
EXR
CCR
PC
*1
*3
*1 *3
REJ09B0139-0400
Section 1 CPU
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