DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 76
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (2Mb)
Section 2 Instruction Descriptions
2.2.7
Bcc (Branch conditionally)
Operation
If condition is true, then
else next;
Assembly-Language Format
Bcc disp
Operand Size
—
Description
If the condition specified in the condition field (cc) is true, a displacement is added to the program
counter (PC) and execution branches to the resulting address. If the condition is false, the next
instruction is executed. The PC value used in the address calculation is the starting address of the
instruction immediately following the Bcc instruction. The displacement is a signed 8-bit or 16-bit
value. The branch destination address can be located in the range from 126 to +128 bytes or
Note: * If the immediately preceding instruction is a CMP instruction, X is the general register contents
Rev. 4.00 Feb 24, 2006 page 60 of 322
REJ09B0139-0400
BRA (BT)
BRN (BF)
BHI
BLS
BCC (BHS)
BCS (BLO)
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
32766 to +32768 bytes from the Bcc instruction.
Mnemonic
PC + disp
Bcc
(destination operand) and Y is the source operand.
Condition field
Always (true)
Never (false)
HIgh
Low or Same
Carry Clear (High or Same)
Carry Set (LOw)
Not Equal
EQual
oVerflow Clear
oVerflow Set
PLus
MInus
Greater or Equal
Less Than
Greater Than
Less or Equal
PC
Meaning
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
cc
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
True
False
C Z = 0
C Z = 1
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
N V = 0
N V = 1
Z (N V) = 0
Z (N V) = 1
Condition
—
I
UI H
—
—
X
X
X
X
X
X = Y (unsigned or signed)
X
X
X
X
—
Y (unsigned)
Y (unsigned)
Y (unsigned)
Y (unsigned)
Y (signed)
Y (signed)
Y (signed)
Y (signed)
Y (unsigned or signed)
U
Signed/Unsigned*
—
N
Conditional Branch
—
Z
— —
V
C
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