PIC16F882-I/SP Microchip Technology, PIC16F882-I/SP Datasheet
PIC16F882-I/SP
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PIC16F882-I/SP Summary of contents
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... PIC16F882/883/884/886/887 28/40/44-Pin, Enhanced Flash-Based 8-Bit © 2009 Microchip Technology Inc. Data Sheet CMOS Microcontrollers with nanoWatt Technology DS41291F ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 nanoWatt Technology Peripheral Features: • 24/35 I/O Pins with Individual Direction Control: - High current source/sink for direct LED drive ...
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... PIC16F882/883/884/886/887 Program Data Memory Memory Device Flash SRAM (words) (bytes) PIC16F882 2048 128 PIC16F883 4096 256 PIC16F884 4096 256 PIC16F886 8192 368 PIC16F887 8192 368 DS41291F-page 2 10-bit A/D ECCP/ I/O (ch) CCP EEPROM (bytes) 128 24 11 1/1 256 24 11 1/1 256 35 14 ...
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... Pin Diagrams – PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP 28-pin PDIP, SOIC, SSOP RE3/MCLR/V PP RA0/AN0/ULPWU/C12IN0- RA1/AN1/C12IN1- RA2/AN2/V -/CV /C2IN+ REF REF RA3/AN3/V +/C1IN+ REF RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT V SS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL TABLE 1: PIC16F882/883/886 28-PIN SUMMARY (PDIP, SOIC, SSOP) I/O Pin Analog ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin QFN 28-pin QFN RA2/AN2/V -/CV /C2IN+ REF REF RA3/AN3/V +/C1IN+ REF RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT V SS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT DS41291F-page RB3/AN9/PGM/C12IN2 RB2/AN8/P1B 3 19 RB1/AN10/P1C/C12IN3- PIC16F882/883/886 4 18 RB0/AN12/INT RC7/RX/ © 2009 Microchip Technology Inc. ...
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... TABLE 2: PIC16F882/883/886 28-PIN SUMMARY (QFN) I/O Pin Analog Comparators RA0 27 AN0/ULPWU C12IN0- RA1 28 AN1 C12IN1- RA2 1 AN2 C2IN+ RA3 2 AN3 C1IN+ RA4 3 — C1OUT RA5 4 AN4 C2OUT RA6 7 — — RA7 6 — — RB0 18 AN12 — RB1 19 AN10 C12IN3- RB2 20 AN8 — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 40-Pin PDIP 40-pin PDIP RE3/MCLR/V PP RA0/AN0/ULPWU/C12IN0- RA1/AN1/C12IN1- RA2/AN2/V -/CV /C2IN+ REF REF RA3/AN3/V +/C1IN+ REF RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/AN5 RE1/AN6 RE2/AN7 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RD0 RD1 DS41291F-page RB7/ICSPDAT 39 RB6/ICSPCLK 2 38 RB5/AN13/T1G RB4/AN11 36 RB3/AN9/PGM/C12IN2 RB2/AN8 6 34 ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin QFN 44-pin QFN RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3- RB2/AN8 DS41291F-page PIC16F884/887 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT © 2009 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin TQFP 44-pin TQFP RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3- RB2/AN8 RB3/AN9/PGM/C12IN2- DS41291F-page PIC16F884/887 RC0/T1OSO/T1CKI RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT © 2009 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... PIC16F882/883/884/886/887 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Memory Organization ................................................................................................................................................................. 21 3.0 I/O Ports ..................................................................................................................................................................................... 39 4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 61 5.0 Timer0 Module ........................................................................................................................................................................... 73 6.0 Timer1 Module with Gate Control............................................................................................................................................... 76 7.0 Timer2 Module ........................................................................................................................................................................... 81 8.0 Comparator Module.................................................................................................................................................................... 83 9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 99 10.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 111 11 ...
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... DEVICE OVERVIEW The PIC16F882/883/884/886/887 is covered by this data sheet. The PIC16F882/883/886 is available in 28- pin PDIP, SOIC, SSOP and QFN packages. The PIC16F884/887 is available in a 40-pin PDIP and 44- pin QFN and TQFP packages. Figure 1-1 shows the block diagram of PIC16F882/883/886 and Figure 1-2 shows a block diagram of the PIC16F884/887 device ...
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... PIC16F882/883/884/886/887 FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM Configuration Flash (2) ( Program Memory Program 14 Bus Instruction Reg Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator Block T1OSI Timer1 32 kHz T1OSO Oscillator T1G T1CKI T0CKI Timer0 Timer1 V + Analog-To-Digital Converter REF (ADC REF ...
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... Oscillator T1G T1CKI T0CKI Timer0 Timer1 V + Analog-To-Digital Converter REF (ADC REF Note 1: PIC16F884 only. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 13 Data Bus Program Counter RAM (1) 8-Level Stack 256 /368 Bytes (13-Bit) File Registers RAM Addr 9 Addr MUX 7 Direct Addr 8 FSR Reg ...
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... PIC16F882/883/884/886/887 TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION Name Function RA0/AN0/ULPWU/C12IN0- RA0 AN0 ULPWU C12IN0- RA1/AN1/C12IN1- RA1 AN1 C12IN1- RA2/AN2/V -/CV /C2IN+ RA2 REF REF AN2 V REF CV REF C2IN+ RA3/AN3/V +/C1IN+ RA3 REF AN3 V + REF C1IN+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C2OUT RA5 AN4 SS C2OUT ...
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... TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED) Name Function RB3/AN9/PGM/C12IN2- RB3 AN9 PGM C12IN2- RB4/AN11/P1D RB4 AN11 P1D RB5/AN13/T1G RB5 AN13 T1G RB6/ICSPCLK RB6 ICSPCLK RB7/ICSPDAT RB7 ICSPDAT RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/P1A/CCP1 RC2 P1A CCP1 RC3/SCK/SCL RC3 ...
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... PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION Name Function RA0/AN0/ULPWU/C12IN0- RA0 AN0 ULPWU C12IN0- RA1/AN1/C12IN1- RA1 AN1 C12IN1- RA2/AN2/V -/CV /C2IN+ RA2 REF REF AN2 V REF CV REF C2IN+ RA3/AN3/V +/C1IN+ RA3 REF AN3 V REF C1IN+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C2OUT RA5 AN4 SS C2OUT ...
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... RD5 P1B RD6/P1C RD6 P1C Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 11. TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ...
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... PIC16F882/883/884/886/887 TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED) Name Function RD7/P1D RD7 P1D RE0/AN5 RE0 AN5 RE1/AN6 RE1 AN6 RE2/AN7 RE2 AN7 RE3/MCLR/V RE3 PP MCLR Legend Analog input or output TTL = TTL compatible input HV = High Voltage DS41291F-page 20 Input Output Type Type TTL CMOS General purpose I/O. ...
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... Program Memory Organization The PIC16F882/883/884/886/887 has a 13-bit program counter capable of addressing (0000h-07FFh) for the PIC16F882 (0000h-0FFFh) for the PIC16F883/PIC16F884, and (0000h-1FFFh) for the PIC16F886/PIC16F887 program memory space. Accessing a location above these boundaries will cause a wrap-around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-2 and 2-3) ...
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... GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the PIC16F882, 256 the PIC16F883/PIC16F884, and 368 the PIC16F886/PIC16F887. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). ...
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... FIGURE 2-4: PIC16F882 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h PORTE 09h TRISE PCLATH 0Ah PCLATH ...
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... PIC16F882/883/884/886/887 FIGURE 2-5: PIC16F883 PIC16F884 SPECIAL FUNCTION REGISTERS / File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC (2) PORTD 08h TRISD PORTE 09h ...
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... Bytes 70h accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. 2: PIC16F887 only. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 File Address Address (1) (1) 80h Indirect addr. 81h TMR0 82h PCL 83h STATUS 84h ...
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... PIC16F882/883/884/886/887 TABLE 2-1: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... TABLE 2-2: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h STATUS ...
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... MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F886/PIC16F887 only. TABLE 2-4: PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... PIC16F882/883/884/886/887 2.2.2.2 OPTION Register The OPTION register, shown in Register 2- readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External INT interrupt • Timer0 • Weak pull-ups on PORTB REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RBPU ...
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... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... PIC16F882/883/884/886/887 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 ADIE RCIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘ ...
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... Disables Ultra Low-Power Wake-up interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables CCP2 interrupt 0 = Disables CCP2 interrupt © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 EEIE ...
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... PIC16F882/883/884/886/887 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 U-0 R/W-0 R-0 ADIF RCIF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘ ...
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... A TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... PIC16F882/883/884/886/887 2.2.2.8 PCON Register The Power Control (PCON) register (see Register 2-8) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR ...
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... Microchip Technology Inc. PIC16F882/883/884/886/887 2.3.2 STACK The PIC16F882/883/884/886/887 devices have an 8-level x 13-bit wide hardware stack (see Figures 2-2 and 2-3). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... PIC16F882/883/884/886/887 FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887 Direct Addressing RP1 RP0 6 From Opcode Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figures 2-2 and 2-3. DS41291F-page 38 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 Indirect Addressing ...
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... PORTA pin configured as an output Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. ...
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... PIC16F882/883/884/886/887 3.2 Additional Pin Functions RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 3.2.1 ANSEL REGISTER The ANSEL register (Register 3-3) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘ ...
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... RC circuit on RA0. See Example 3-2 for initializing the Ultra Low-Power Wake-up module. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/ULPWU/C12IN0- pin and can allow for software calibration of the time-out (see Figure 3-1) ...
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... PIC16F882/883/884/886/887 3.2.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D Converter (ADC), refer to the appropriate section in this data sheet. ...
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... PORTA To Comparator To A/D Converter Note 1: ANSEL determines Analog Input mode. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 3.2.3.3 RA2/AN2/V Figure 3-3 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • ...
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... PIC16F882/883/884/886/887 3.2.3.4 RA3/AN3/V +/C1IN+ REF Figure 3-4 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose input • an analog input for the ADC • a positive voltage reference input for the ADC and CV REF • a positive analog input to Comparator C1 ...
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... PORTA To SS Input To A/D Converter Note 1: ANSEL determines Analog Input mode. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 3.2.3.7 RA6/OSC2/CLKOUT Figure 3-7 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • ...
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... PIC16F882/883/884/886/887 3.2.3.8 RA7/OSC1/CLKIN Figure 3-8 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • a clock input FIGURE 3-8: BLOCK DIAGRAM OF RA7 Oscillator Data Bus Circuit OSC1 PORTA TRISA INTOSC ...
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... The following three sections describe these PORTB pin functions. Every PORTB pin on this device family has an interrupt-on-change option and a weak pull-up option. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 3.4.1 ANSELH REGISTER The ANSELH register (Register 3-4) is used to configure the Input mode of an I/O pin to analog. ...
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... PIC16F882/883/884/886/887 REGISTER 3-4: ANSELH: ANALOG SELECT HIGH REGISTER U-0 U-0 R/W-1 — — ANS13 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANS<13:8>: Analog Select bits Analog select between analog or digital function on pins AN<13:8>, respectively. ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... Figure 3-9 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (1) • a PWM output Note 1: P1B is available on PIC16F882/883/886 only. 3.4.4.4 RB3/AN9/PGM/C12IN2- Figure 3-9 shows the diagram for this pin. This pin is configurable to function as one of the following: • ...
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... Figure 3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (1) • a PWM output Note 1: P1D is available on PIC16F882/883/886 only. 3.4.4.6 RB5/AN13/T1G Figure 3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • ...
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... PIC16F882/883/884/886/887 TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 ANSELH — — ANS13 CCP1CON P1M1 P1M0 DC1B1 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL IOCB IOCB7 IOCB6 IOCB5 INTCON GIE PEIE T0IE OPTION_REG RBPU INTEDG T0CS PORTB RB7 RB6 RB5 ...
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... PORTC pin configured as an output Note 1: TRISC<1:0> always reads ‘1’ Oscillator mode. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISC register (Register 3-10) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the ...
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... PIC16F882/883/884/886/887 3.5.1 RC0/T1OSO/T1CKI Figure 3-11 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 oscillator output • a Timer1 clock input FIGURE 3-11: BLOCK DIAGRAM OF RC0 Data Bus Timer1 Oscillator T1OSCEN Circuit ...
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... Q PORTC TRISC RD TRISC RD PORTC To SSPSR © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 3.5.6 RC5/SDO Figure 3-16 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a serial data output FIGURE 3-16: Data Bus PORTC ...
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... PIC16F882/883/884/886/887 3.5.7 RC6/TX/CK Figure 3-17 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial output • a synchronous clock I/O FIGURE 3-17: BLOCK DIAGRAM OF RC6 SPEN TXEN SYNC EUSART Data Bus ...
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... PORTD pin configured as an input (tri-stated PORTD pin configured as an output © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISD register (Register 3-12) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the ...
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... Figure 3-20 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a PWM output Note 1: RD6/P1C is available on PIC16F884/887 only. See RB1/AN10/P1C/C12IN3- for this function on PIC16F882/883/886. 3.6.4 RD7/P1D Figure 3-20 shows the diagram for this pin. This pin is configurable to function as one of the following • ...
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... PORTE pin configured as an output Note 1: TRISE<3> always reads ‘1’. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISE register (Register 3-14) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs ...
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... PIC16F882/883/884/886/887 (1) 3.7.1 RE0/AN5 This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC Note 1: RE0/AN5 is available on PIC16F884/887 only. (1) 3.7.2 RE1/AN6 This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC Note 1: RE1/AN6 is available on PIC16F884/887 only ...
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... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... PIC16F882/883/884/886/887 4.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 4-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...
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... Upon restarting the external clock, the device will resume operation time had elapsed. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 4.4 External Clock Modes 4.4.1 OSCILLATOR START-UP TIMER (OST) ...
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... PIC16F882/883/884/886/887 4.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...
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... The user also needs to take into account variation due to tolerance of external RC components used. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 4.5 Internal Clock Modes The oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
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... PIC16F882/883/884/886/887 4.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...
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... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 4.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 4-6) ...
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... PIC16F882/883/884/886/887 FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC ≠ 0 IRCF <2:0> System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC ≠ IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <2:0> ...
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... OSTS bit of the OSCCON register to remain clear. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 When the oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...
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... PIC16F882/883/884/886/887 4.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 4.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
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... PIC16F882/883/884/886/887 FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...
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... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word Register1. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 ...
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... PIC16F882/883/884/886/887 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
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... TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘ ...
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... PIC16F882/883/884/886/887 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...
Page 79
... The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...
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... PIC16F882/883/884/886/887 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • ...
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... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...
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... PIC16F882/883/884/886/887 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 CM2CON1 MC1OUT MC2OUT C1RSEL INTCON GIE PEIE T0IE PIE1 — ADIE RCIE PIR1 — ADIF RCIF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L ...
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... T2CKPS<1:0> © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... PIC16F882/883/884/886/887 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
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... Programmable and fixed voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 8.1 Comparator Overview A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at V less than the analog voltage at V comparator is a digital low level ...
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... PIC16F882/883/884/886/887 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C12IN0- 0 C12IN1- 1 MUX C12IN2- 2 C12IN3- 3 C1R C1IN+ 0 MUX FixedRef 1 0 MUX CV REF C1V REF 1 C1R SEL Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate and Q3 are phases of the four-phase system clock ( held high during Sleep mode ...
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... CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note 1: The CxOE bit overrides the PORT data control and latch. Setting the CxON has no impact on the port override ...
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... PIC16F882/883/884/886/887 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive- or gate (see Figures 8-2 and 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read ...
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... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their Off states. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 DS41291F-page 87 ...
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... PIC16F882/883/884/886/887 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 C1ON C1OUT C1OE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit ...
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... C12IN2- pin of C2 connects to C2V 11 = C12IN3- pin of C2 connects to C2V Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > ...
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... PIC16F882/883/884/886/887 8.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their con- nection with a digital input, they have reverse biased ESD protection diodes to V and V DD input, therefore, must be between V SS input voltage deviates from this range by more than 0 ...
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... Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit 1 = Output is synchronous to falling edge of Timer1 clock 0 = Output is asynchronous © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register ...
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... PIC16F882/883/884/886/887 8.9 Comparator SR Latch The SR latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs. The SR latch may also be set or reset, independent of comparator output, by control bits in the SRCON control register ...
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... The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/S-0 R/S-0 C2REN PULSS ...
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... The voltage source is selectable through both ends of the 16 connection resistor ladder network. Bit VRSS of the VRCON register selects either the internal or external voltage source. The PIC16F882/883/884/886/887 allows the CV signal to be output to the RA2 pin of PORTA under certain configurations only. For more details, see Figure 8-9. ...
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... C2RSEL FixedRef 0.6V To Comparators and ADC Module FIGURE 8-9: COMPARATOR AND ADC VOLTAGE REFERENCE BLOCK DIAGRAM V + REF VROE VCFG1 VRSS REF © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 16 Stages Analog MUX 15 0 VR<3:0> Fixed Voltage Reference AV DD VRSS CV REF Comparator Voltage Reference ...
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... PIC16F882/883/884/886/887 TABLE 8-2: COMPARATOR AND ADC VOLTAGE REFERENCE PRIORITY Comp. RA3 RA2 Reference (+) Reference (-) I REF REF REF REF REF REF REF V + I/O AV REF REF REF REF REF REF REF REF REF I REF DD I REF REF REF REF REF REF ...
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... TRISB6 TRISB5 VRCON VREN VROE VRR Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 VRSS VR3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared -/CV ...
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... PIC16F882/883/884/886/887 NOTES: DS41291F-page 98 © 2009 Microchip Technology Inc. ...
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... AN7 0111 1000 AN8 1001 AN9 1010 AN10 AN11 1011 AN12 1100 1101 AN13 CVREF 1110 FixedRef 1111 CHS<3:0> © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 (ADC) allows VCFG1 = VCFG1 = VCFG0 = 0 VCFG0 = 1 ADC GO/DONE ADFM ADON Left Justify 1 = Right Justify 10 ADRESH ADRESL ...
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... PIC16F882/883/884/886/887 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 14.3 “Interrupts” for more information. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V Device Frequency (F 20 MHz ...
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... PIC16F882/883/884/886/887 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ...
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... See Section 9.3 “A/D Requirements”. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. ; ;Conversion start & polling for completion ...
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... PIC16F882/883/884/886/887 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the opera- tion of the ADC. Note: For ANSEL and ANSELH registers, see Register 3-3 and Register 3-4, respectively. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS3 ...
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... REF bit 4 VCFG0: Voltage Reference bit pin REF bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 U-0 U-0 VCFG0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 0 ...
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... PIC16F882/883/884/886/887 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ...
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... The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC) ...
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... PIC16F882/883/884/886/887 FIGURE 9-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD Note 1: See Section 17.0 “Electrical Specifications”. FIGURE 9-5: ADC TRANSFER FUNCTION ...
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... TRISB TRISB7 TRISB6 TRISB5 TRISE — — — Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE VCFG0 — — ...
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... PIC16F882/883/884/886/887 NOTES: DS41291F-page 110 © 2009 Microchip Technology Inc. ...
Page 113
... EEADR and EEADRH registers form a 2-byte word that holds the 12-bit address of the EEPROM location being read. The PIC16F882 devices have 2K words of program EEPROM with an address range from 0h to 07FFh. The PIC16F883/PIC16F884 devices have 4K words of program EEPROM with an address range from 0h to 0FFFh ...
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... PIC16F882/883/884/886/887 REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory ...
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... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC16F882/883/884/886/887 10.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction ...
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... MOVWF HIGHPMBYTE BCF STATUS, RP1 © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 EEDAT and EEDATH registers will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set ...
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... PIC16F882/883/884/886/887 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDAT Register EERHLT DS41291F-page 116 EEADRH,EEADR PC+3 INSTR ( EEDATH,EEDAT INSTR ( INSTR( Forced NOP executed here executed here INSTR ( ...
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... Microchip Technology Inc. PIC16F882/883/884/886/887 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set ...
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... PIC16F882/883/884/886/887 FIGURE 10-2: BLOCK WRITES TO 2K AND 4K FLASH PROGRAM MEMORY First word of block to be written 14 EEADR<1:0> EEADR<1:0> Buffer Register FIGURE 10-3: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY First word of block to be written 14 EEADR<2:0> = 000 EEADR<2:0> = 001 Buffer Register DS41291F-page 118 EEDATH ...
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... Indicates when sixteen words have been programmed SUBLW 0x0F ; ; ; ; BTFSS STATUS,Z ; Exit on a match, GOTO LOOP ; Continue if more data needs to be written © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Required Sequence 0x0F = 16 words 0x0B = 12 words (PIC16F884/883/882 only) 0x07 = 8 words 0x03 = 4 words(PIC16F884/883/882 only) DS41291F-page 119 ...
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... PIC16F882/883/884/886/887 10.3 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-5) to the desired value to be written. EXAMPLE 10-5: WRITE VERIFY BANKSEL EEDAT ; MOVF EEDAT, W ;EEDAT not changed ;from previous write BANKSEL EECON1 ...
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... OSFIF C2IF C1IF Legend unknown unchanged, — = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: PIC16F886/PIC16F887 only. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 — WRERR WREN WR EEADR4 EEADR3 ...
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... PIC16F882/883/884/886/887 NOTES: DS41291F-page 122 © 2009 Microchip Technology Inc. ...
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... Enhanced PWM features available on CCP1 only. See Section 11.6 “PWM (Enhanced Mode)” for more information. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 this DS41291F-page 123 ...
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... PIC16F882/883/884/886/887 11.1 Enhanced Capture/Compare/PWM (CCP1) The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired ...
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... Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP2 pin is unaffected.) 11xx = PWM mode. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 TABLE 11-2: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode ...
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... PIC16F882/883/884/886/887 11.3 Capture Mode In Capture mode, the CCPRxH, CCPRxL register pair captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • ...
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... Clearing the CCP1CON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 11.4.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...
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... PIC16F882/883/884/886/887 11.5 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPRxL • CCPxCON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCPx pin ...
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... Note: The Timer2 postscaler (see Section 7.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 11.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB< ...
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... PIC16F882/883/884/886/887 11.5.3 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255 ...
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... EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 11.5.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
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... PIC16F882/883/884/886/887 11.6 PWM (Enhanced Mode) The Enhanced PWM Mode can generate a PWM signal four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • Single PWM • Half-Bridge PWM • Full-Bridge PWM, Forward mode • Full-Bridge PWM, Reverse mode To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately ...
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... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 “Programmable Dead-Band Delay Mode”). © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Pulse 0 Width Period (1) (1) Delay Delay PR2+1 ...
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... PIC16F882/883/884/886/887 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> (Single Output) P1A Modulated 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active (Full-Bridge, P1B Inactive 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • ...
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... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 11-8: ...
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... PIC16F882/883/884/886/887 11.6.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 11-11. ...
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... Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Period (1) Period (1) DS41291F-page 137 ...
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... PIC16F882/883/884/886/887 11.6.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. ...
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... External Switch D Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Forward Period Reverse Period OFF – T ...
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... PIC16F882/883/884/886/887 11.6.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external cir- ...
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... From Comparator C1 001 000 © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state ...
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... PIC16F882/883/884/886/887 REGISTER 11-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state ...
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... FIGURE 11-16: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Period Shutdown Shutdown Event Occurs Event Clears ...
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... PIC16F882/883/884/886/887 11.6.6 PROGRAMMABLE DEAD-BAND DELAY MODE In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off ...
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... Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM bit 6-0 PDC<6:0>: PWM Delay Count bits PDCn = Number of F should transition active and the actual time it transitions active. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F882/883/884/886/887 11.6.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode (CCP1M<3:2> and P1M<1:0> CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR< ...
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... Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 P1A pin P1B pin P1C pin P1D pin DS41291F-page 147 ...
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... PIC16F882/883/884/886/887 11.6.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1< ...
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... TRISB5 TRISC TRISC7 TRISC6 TRISC5 TRISD TRISD7 TRISD6 TRISD5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the PWM. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 DC2B0 CCP2M3 ...
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... PIC16F882/883/884/886/887 NOTES: DS41291F-page 150 © 2009 Microchip Technology Inc. ...
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... SPBRG BRGH BRG16 © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
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... PIC16F882/883/884/886/887 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 + 1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • ...
Page 155
... I/O function must be disabled by clearing the corresponding ANSEL bit. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the EUSART receiver is enabled ...
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... PIC16F882/883/884/886/887 12.1.1.4 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...
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... TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RBIE ...
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... PIC16F882/883/884/886/887 12.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 12-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate ...
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... FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 12.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...
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... PIC16F882/883/884/886/887 12.1.2.8 Asynchronous Reception Set-up: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 12.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation ...
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... TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE RBIE ...
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... PIC16F882/883/884/886/887 12.2 Clock Accuracy with Asynchronous Operation The factory calibrates the Internal Oscillator block out- put (INTOSC). However, the INTOSC frequency may drift temperature changes, and this directly DD affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
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... PIC16F882/883/884/886/887 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 ABDOVF RCIDL — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’ ...
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... Legend unknown unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
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... PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES F = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1221 1.73 255 2400 2404 0.16 129 9600 9470 -1.36 32 10417 10417 0.00 29 10286 19.2k 19.53k 1 ...
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... Microchip Technology Inc. PIC16F882/883/884/886/887 SYNC = 0, BRGH = 1, BRG16 = 3.6864 MHz F = 2.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
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... PIC16F882/883/884/886/887 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 300.0 0.00 16665 1200 1200 -0.01 4166 2400 2400 0.02 2082 9600 9597 -0 ...
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... Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...
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... PIC16F882/883/884/886/887 12.3.2 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. ...
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... After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends 12.3.4 ...
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... PIC16F882/883/884/886/887 FIGURE 12-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here SENDB (send Break control bit) DS41291F-page 170 bit 0 bit 1 ...
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... One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 12.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCTL register ...
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... PIC16F882/883/884/886/887 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT bit 0 bit 1 pin Word 1 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. ...
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... CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. ...
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... PIC16F882/883/884/886/887 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT bit 0 pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit ‘0’ CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. ...
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... TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...
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... PIC16F882/883/884/886/887 12.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 12.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep ...
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... SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 12.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • ...
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... PIC16F882/883/884/886/887 NOTES: DS41291F-page 178 © 2009 Microchip Technology Inc. ...
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... These include a STATUS register and two control registers. Register 13-1 shows the MSSP STATUS register (SSPSTAT), Register 13-2 shows the MSSP Control Register 1 (SSPCON), and Register 13-3 shows the MSSP Control Register 2 (SSPCON2). © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 DS41291F-page 179 ...
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... PIC16F882/883/884/886/887 REGISTER 13-1: SSPSTAT: SSP STATUS REGISTER R/W-0 R/W-0 R-0 SMP CKE D/A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SMP: Sample bit SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time ...
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... I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ...
Page 184
... PIC16F882/883/884/886/887 REGISTER 13-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0 R-0 R/W-0 GCEN ACKSTAT ACKDT bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 GCEN: General Call Enable bit ( Enable interrupt when a general call address (0000h) is received in the SSPSR ...
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... Clock edge (output data on rising/falling edge of SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) Figure 13-1 shows the block diagram of the MSSP module, when in SPI mode. © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 FIGURE 13-1: Read SDI bit 0 SDO SS Control ...
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... PIC16F882/883/884/886/887 When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The buffer full bit BF of the SSPSTAT register indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared ...
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... SSPIF SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The clock polarity is selected by appropriately program- ming the CKP bit of the SSPCON register. This, then, would give waveforms for SPI communication as shown in Figure 13-2, Figure 13-4 and Figure 13-5, where the MSb is transmitted first. In Master mode, the ...
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... PIC16F882/883/884/886/887 13.3.4 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit of the PIR1 register is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications ...
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... SCK (CKP = 1 CKE = 1) Write to SSPBUF bit 7 SDO SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 ...
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... PIC16F882/883/884/886/887 13.3.6 SLEEP OPERATION In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device ...
Page 191
... MSSP Shift Register (SSPSR) – Not directly accessible • MSSP Address register (SSPADD) • MSSP Mask register (SSPMSK) © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 The SSPCON register allows control of the I operation. The SSPM<3:0> mode selection bits (SSPCON register) allow one of the following selected: 2 • ...
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... PIC16F882/883/884/886/887 13.4.1.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register ...
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... BF SSPOV 2 FIGURE 13-8: I C™ SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data in Sampled SSPIF BF CKP © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full ...
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... PIC16F882/883/884/886/887 13.4.2 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that, the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
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... SDA SDA In SCL SCL In Bus Collision Note: I/O pins have diode protection to V © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 2 13.4.4 I C™ MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is enabled, the user has the following six options: 1 ...
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... PIC16F882/883/884/886/887 2 13.4.4.1 I C™ Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG 03h Value BRG Reload © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 ) on the CY SSPM<3:0> SSPADD<6:0> Reload Reload Control BRG Down Counter CLKOUT DX-1 SCL allowed to transition high ...
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... PIC16F882/883/884/886/887 2 13.4.6 I C™ MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Con- dition Enable bit SEN of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the SSPADD<6:0> and starts its count. If SCL and SDA are ...
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... SDA = 1, SCL (no change) SDA Falling edge of ninth clock End of Xmit SCL © 2009 Microchip Technology Inc. PIC16F882/883/884/886/887 Note 1: If RSEN is programmed while any other event is in progress, it will not take effect bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • ...
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... PIC16F882/883/884/886/887 2 13.4.8 I C™ MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the SSPBUF register. This action will set the Buffer Full bit, BF, and allow the Baud Rate Generator to begin counting and start the next trans- mission ...