PIC18F14K50-I/P Microchip Technology, PIC18F14K50-I/P Datasheet - Page 283

• Manufacturer Part Number: PIC18F14K50-I/P
• Description: IC PIC MCU FLASH 8KX16 20-PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/P

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 20PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.5
PIC18F/LF1XK50 devices incorporate three separate
on-chip timers that help regulate the Power-on Reset
process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
23.5.1
The Power-up Timer (PWRT) of PIC18F/LF1XK50
devices is an 11-bit counter which uses the LFIN-
TOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 s = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See Section 27.0 “Electrical
Specifications” for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
TABLE 23-2:
 2010 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
Configuration
2: 2 ms is the nominal time required for the PLL to lock.
Oscillator
Device Reset Timers
POWER-UP TIMER (PWRT)
TIME-OUT IN VARIOUS SITUATIONS
66 ms
66 ms
(1)
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
Power-up
OSC
(1)
(1)
(1)
+ 2 ms
OSC
Preliminary
(2)
(2)
and Brown-out
23.5.2
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from all power-managed modes that stop the external
oscillator.
23.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.
23.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 23-3,
Figure 23-4, Figure 23-5, Figure 23-6 and Figure 23-7
all depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 23-3 through 23-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program
execution to begin immediately (Figure 23-5). This is
useful for testing purposes or to synchronize more than
one PIC18F1XK50/PIC18LF1XK50 device operating in
parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
OSC
—
—
—
PIC18F/LF1XK50
OSCILLATOR START-UP TIMER
(OST)
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
OSC
(2)
PLL
) is typically 2 ms and follows
Power-Managed Mode
1024 T
DS41350D-page 283
1024 T
Exit from
OSC
—
—
—
+ 2 ms
OSC
(2)