PIC18F14K50-I/P Microchip Technology, PIC18F14K50-I/P Datasheet - Page 41

• Manufacturer Part Number: PIC18F14K50-I/P
• Description: IC PIC MCU FLASH 8KX16 20-PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/P

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/MSSP/SPI/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 20PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-2:
 2010 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
Legend:
Note
File Name
1:
2:
3:
Top-of-Stack, High Byte (TOS<15:8>)
Top-of-Stack, Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC, Low Byte (PC<7:0>)
Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register, High Byte
Product Register, Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
Indirect Data Memory Address Pointer 0, Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value
of FSR1 offset by W
Indirect Data Memory Address Pointer 1, Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value
of FSR2 offset by W
Indirect Data Memory Address Pointer 2, Low Byte
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 23.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
Bits RA0 and RA1 are available only when USB is disabled.
GIE/GIEH
STKFUL
RABPU
INT2IP
Bit 7
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F/LF1XK50)
PEIE/GIEL
INTEDG0
STKUNF
INT1IP
Bit 6
—
—
—
—
—
—
—
—
INTEDG1
TMR0IE
Bit 5
—
—
—
—
—
—
—
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT2IE
INT0IE
Bit 4
SP4
—
—
—
—
N
Preliminary
Indirect Data Memory Address Pointer 0, High Byte
Indirect Data Memory Address Pointer 1, High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2, High Byte
INT1IE
RABIE
Bit 3
SP3
OV
—
TMR0IF
TMR0IP
Bit 2
SP2
—
Z
PIC18F/LF1XK50
INT0IF
INT2IF
Bit 1
SP1
DC
—
RABIP
INT1IF
RABIF
Bit 0
SP0
C
DS41350D-page 41
---0 0000 287, 30
0000 0000 287, 30
0000 0000 287, 30
00-0 0000 287, 31
---0 0000 287, 30
0000 0000 287, 30
0000 0000 287, 30
---0 0000 287, 54
0000 0000 287, 54
0000 0000 287, 54
0000 0000 287, 54
xxxx xxxx 287, 65
xxxx xxxx 287, 65
0000 000x 287, 69
1111 -1-1 287, 70
11-0 0-00 287, 71
---- 0000 287, 47
xxxx xxxx 287, 47
xxxx xxxx
---- 0000 288, 47
xxxx xxxx 288, 47
---- 0000 288, 35
---- 0000 288, 47
xxxx xxxx 288, 47
---x xxxx 288, 45
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details
287, 47
287, 47
287, 47
287, 47
287, 47
287, 47
287, 47
287, 47
287, 47
287, 47
288, 47
288, 47
288, 47
288, 47
288, 47
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