PIC18F1320-I/ML Microchip Technology, PIC18F1320-I/ML Datasheet - Page 19

• Manufacturer Part Number: PIC18F1320-I/ML
• Description: IC MCU FLASH 4KX16 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/ML

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• On-chip Adc: 7-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.6
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.5 “ID
Location Programming”).
The code sequence detailed in Table 3-6 should be
used, except that the address data used in “Step 2” will
be in the range of 000000h to 0001FFh.
TABLE 3-7:
FIGURE 3-9:
 2010 Microchip Technology Inc.
Step 1: Direct access to configuration memory.
Step 2: Position the program counter.
Step 3: Set Table Pointer for Configuration Word to be written. Write even/odd addresses.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
4-Bit
2:
Boot Block Programming
If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table writes. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 0x100000).
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration
bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
8E A6
8C A6
EF 00
F8 00
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
CONFIGURATION PROGRAMMING FLOW
Data Payload
Delay P9 Time
Configuration
Load Even
for Write
Program
Address
Done
Start
LSB
(1)
BSF
BSF
GOTO
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF
Load 2 bytes and start programming
NOP - hold PGC high for time P9
EECON1, EEPGD
EECON1, CFGS
0x100000
TBLPTRL
3.7
Unlike code memory, the Configuration bits are
programmed a byte at a time. The “Table Write, Begin
Programming” 4-bit command (1111) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code
configuration locations is shown in Table 3-7.
sequence
PIC18FX220/X320
Core Instruction
Configuration Bits Programming
Delay P9 Time
Configuration
Load Odd
for Write
Program
Address
Done
Start
MSB
to
program
two
DS39592F-page 19
consecutive